Resistance dividing circuit and manufacturing method thereof
View Patent ↗A resistance dividing circuit including silicide layers respectively formed only on branch portions of a linear polysilicon resistance wiring having the branch portions. Contact plugs are connected to the resistance wiring via the silicide layers, and fetching electrodes are respectively connected to the contact plugs.
1. A resistance element comprising:
a polysilicon pattern formed on a semiconductor substrate, said polysilicon pattern having a main portion and a plurality of branch portions protruded from the main portion;
an insulating layer formed so as to cover the semiconductor substrate and said polysilicon pattern and having a plurality of contact holes defined therein, each of the contact holes being located over a corresponding branch portion;
a plurality of contact plugs formed within the contact holes;
a wiring pattern formed on said contact plug and said insulating layer; and
a silicide layer formed between said contact plug and said polysilicon pattern,
wherein a silicide layer is not formed on the main portion of said polysilicon pattern.
2. The resistance element according to claim 1 , wherein said polysilicon pattern has a plurality of bend portions.
3. The resistance element according to claim 1 , wherein said polysilicon pattern has a first straight portion extending in a first direction and a second straight portion extending in a second direction perpendicular to the first direction.
4. A resistance element comprising:
a polysilicon pattern formed on a semiconductor substrate, said polysilicon pattern having a trunk portion and a plurality of branch portions;
an insulating layer formed so as to cover the semiconductor substrate and said polysilicon pattern and having a plurality of contact holes defined therein, each of the contact holes being located over a corresponding branch portion;
a plurality of contact plugs formed within the contact holes;
a wiring pattern formed on said contact plug and said insulating layer; and
a silicide layer formed between said contact plug and said polysilicon pattern,
wherein a silicide layer is not formed on the trunk portion of said polysilicon pattern.
5. The resistance element according to claim 4 , wherein said polysilicon pattern has a plurality of bend portions.
6. The resistance element according to claim 4 , wherein said polysilicon pattern has a first straight portion extending in a first direction and a second straight portion extending in a second direction perpendicular to the first direction.
7. A resistance element comprising:
a polysilicon pattern formed on a semiconductor substrate, said polysilicon pattern having a main portion and a plurality of branch portions protruded from the main portion;
an insulating layer formed so as to cover the semiconductor substrate and said polysilicon pattern and having a plurality of contact holes defined therein, each of the contact holes corresponding to a predetermined area of the branch portions;
a silicide layer formed on the predetermined areas of the branch portions;
a contact plug formed on the silicide layer; and
a wiring pattern formed on said contact plug and said insulating layer,
wherein a silicide layer is not formed on the main portion of said polysilicon pattern.
8. The resistance element according to claim 7 , wherein said polysilicon pattern has a plurality of bend portions.
9. The resistance element according to claim 7 , wherein said polysilicon pattern has a first straight portion extending in a first direction and a second straight portion extending in a second direction perpendicular to the first direction.
10. A method for manufacturing a resistance element, comprising:
forming a polysilicon pattern on a semiconductor substrate, said polysilicon pattern having a main portion and a plurality of branch portions:
depositing a metal layer on said polysilicon pattern to form a silicide layer on a surface of said polysilicon pattern;
removing the silicide layer on said main portion so that the silicide layer remains on said branch portions;
forming an insulating layer over the semiconductor substrate and said polysilicon pattern;
forming contact holes in said insulating layer to expose said silicide layer;
forming contact plugs on said silicide layer; and
forming a wiring pattern on said contact plug and said insulating layer.