IP Library Granted Patent US 7,608,476
Granted Patent B2
US 7,608,476 · App. 11/596,211 · Granted Oct 27, 2009

Electronic device

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Quick Facts
Patent No.
US 7,608,476
App. No.
11/596,211
Granted
Oct 27, 2009
Kind
B2
Abstract

A technique for high-resolution surface energy assisted patterning of semiconductor active layer islands on top of an array of predefined source-drain electrodes without requiring an additional process step for surface energy patterning.

Claims (37)

1. A method of forming an electronic device including spaced apart bodies of electrically conductive material connected by a channel of semiconductive material, the method including the steps of: forming said spaced apart bodies of electrically conductive material on a substrate; and using said bodies to control the deposition of a liquid including said semiconductive material or a precursor thereto to form said semiconductive channel wherein said electrically conductive bodies are formed by depositing conductive material or a precursor thereto on the substrate, and then removing selected portions of the deposited conductive material or precursor thereto.

2. A method according to claim 1 , wherein said semiconductive material is essentially absent from the region of the substrate surrounding said bodies of electrically conductive material except in said channel.

3. A method according to claim 1 , using the surface wetting properties of said bodies with respect to those of the bare substrate to confine the deposition of said liquid.

4. A method according to claim 3 , wherein the relative attractive properties of the surface of said electrically conductive bodies are used to confine said liquid to a region of said conductive bodies and said channel.

5. A method according to claim 4 , wherein the surface of said bodies has a greater attraction for said liquid than the surface of the portion of the substrate in the space between said bodies.

6. A method according to claim 3 , wherein the surface of said bodies has a lesser attraction for said liquid than the surface of the portion of the substrate in the space between said bodies.

7. A method as claimed in claim 1 , wherein said semiconductive channel is formed across a spacing of less than 50 microns between said bodies.

8. A method as claimed in claim 7 , wherein said semiconductive channel is formed across a spacing of less than 20 microns between said bodies.

9. A method according to claim 1 , wherein said substrate including said conductive bodies is exposed to a surface modification treatment prior to the deposition of said liquid, which changes the relative wetting properties of the surface of said conductive bodies relative to that of the bare substrate, and defines a surface energy pattern on the substrate, which is then used to control the deposition of said liquid including said semiconductive material or a precursor thereto.

10. A method according to claim 9 , wherein said surface modification treatment comprises exposing the substrate and said electrically conductive bodies to a material that reacts selectively with either the substrate or the said electrically conductive bodies or adheres selectively to either the substrate or said electrically conductive bodies.

11. A method according to claim 9 , wherein the surface modification process includes exposing the substrate and said bodies to a plasma and/or immersing the substrate and said bodies into a bath of surface modification agent.

12. A method according to claim 9 , wherein the surface modification step includes selectively increasing the attraction of the surface of said bodies for said liquid.

13. A method according to claim 9 , wherein the surface modification step includes selectively decreasing the attraction of the surface of the substrate for said liquid.

14. A method according to claim 9 , wherein the surface modification step includes selectively decreasing the attraction of the surface of said bodies for said liquid.

15. A method according to claim 1 , wherein said liquid is substantially confined to an area defined by the outer edges of said bodies.

16. A method as claimed in claim 1 , wherein the surface tension of said liquid is higher than 25 dyn/cm.

17. A method as claimed in claim 1 , wherein the surface tension of said liquid is higher than 28 dyn/cm.

18. A method as claimed in claim 1 , wherein the surface tension of said liquid is higher than 30 dyn/cm.

19. A method as claimed in claim 1 , wherein the viscosity of said liquid is higher than 5 cP.

20. A method as claimed in claim 1 , wherein the viscosity of said liquid is higher than 10 cP.

21. A method according to claim 1 , further including the step of forming on the substrate at least one structure of said electrically conductive material in addition to said spaced apart bodies to assist the deposition of said liquid on the substrate in the space between said two electrically conductive bodies.

22. A method according to claim 21 , wherein said liquid is substantially confined to an area defined by the outer edges of said bodies and said further structures.

23. A method according to claim 21 , wherein said further structures do not function in the operation of the electronic device.

24. A method according to claim 1 , wherein said electrically conductive bodies are formed on the substrate by a patterning step.

25. A method according to claim 1 , wherein selected portions of the deposited conductive material are removed using a process of laser ablation.

26. A method according to claim 25 , wherein selected portions of the deposited conductive material are removed using a process of photolithography.

27. A method according to claim 1 , wherein the substrate includes a gate electrode and an overlying dielectric layer, and said electrically conductive bodies are formed on the overlying dielectric layer to define source and drain electrodes.

28. A method according to claim 1 , further including the steps of: forming a dielectric layer on the semiconducting channel and forming a gate electrode on the dielectric layer to thereby define together with said electrically conductive bodies and said semiconductive channel a field-effect transistor.

29. An electronic device produced by a method according to claim 1 .

30. An integrated circuit including a plurality of electronic devices according to claim 29 .

31. A method of forming an electronic device including spaced apart bodies of electrically conductive material connected by a channel of semiconductive material, the method including the steps of:

forming said spaced apart bodies of electrically conductive material on a substrate;

forming on the substrate at least one structure in addition to said spaced apart bodies of said electrically conductive material; and

using said bodies to control the deposition of a liquid including said semiconductive material or a precursor thereto to form said semiconductive channel;

wherein said at least one structure facilitates the deposition of said liquid on the substrate in the space between said two electrically conductive spaced-apart bodies.

32. A method according to claim 31 , wherein said liquid is substantially confined to an area defined by the outer edges of said bodies and said further structures.

33. A method according to claim 31 , wherein said further structures do not function in the operation of the electronic device.

Assignments (5)
CHANGE OF NAME Recorded May 5, 2016
From: PLASTIC LOGIC LIMITED
To: FLEXENABLE LIMITED
Reel/Frame 038617/0662 →
RELEASE OF SECURITY INTEREST Recorded May 12, 2011
From: STATE CORPORATION "RUSSIAN CORPORATION OF NANOTECHNOLOGIES"
To: PLASTIC LOGIC LIMITED
Reel/Frame 026271/0377 →
SECURITY AGREEMENT Recorded Aug 3, 2010
From: PLASTIC LOGIC LIMITED
To: STATE CORPORATION "RUSSIAN CORPORATION OF NANOTECHNOLOGIES"
Reel/Frame 024776/0357 →
RECORD TO CORRECT THE EXECUTION DATE OF THE FIRST ASIGNOR ON REEL 019343 FRAME 0424 Recorded Jun 22, 2007
From: RAMSDALE, CATHERINE MARY; SIRRINGHAUS, HENNING; VON WERNE, TIMOTHY ALLAN
To: PLASTIC LOGIC LIMITED
Reel/Frame 019523/0717 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2007
From: RAMSDALE, CATHERINE MARY; SIRRINGHAUS, HENNING; VON WERNE, TIMOTHY ALLAN
To: PLASTIC LOGIC LIMITED
Reel/Frame 019343/0424 →