Microprocessor and Method of Instruction Alignment
Therefore, a microprocessor for processing instructions is provided. Said microprocessor comprises a cache for caching instructions and/or data to be processed, which are arranged in cache words, and an alignment unit for aligning instructions to predetermined positions with regard to cache word boundaries of said cache by introducing padding bytes (padd 1, padd 2 ). At least one of said padding bytes (padd 1, padd 2 ) include static data, which are required within the processing of one of said instructions. Accordingly, the padding bytes which are required for the alignment of the instructions, can be utilized for data which is needed during the processing of the instruction such that these bytes are not wasted and the available storage capacity is efficiently used.
1 . Microprocessor for processing instructions, comprising:
at least one cache for caching instructions and/or data to be processed, which are arranged in cache words, and
an alignment unit for aligning instructions to predetermined positions with regard to cache word boundaries of said cache by introducing padding bytes (padd 1 , padd 2 ),
wherein at least one of said padding bytes (padd 1 , padd 2 ) include static data, which are required within the processing of one of said instructions.
2 . Microprocessor according to claim 1 , wherein
said alignment unit is further adapted to align branch targets by introducing padding bytes.
3 . Microprocessor according to claim 2 , wherein
said static data comprise global variables or constants.
4 . Method for instruction alignment during the processing of instructions, comprising the steps of:
caching instructions and/or data to be processed, which are arranged in cache words, and
aligning instructions to predetermined positions with regard to cache word boundaries by introducing padding bytes (padd 1 , padd 2 ),
wherein at least one of said padding bytes (padd 1 , padd 2 ) include static data, which are required within the processing of one of said instructions.
5 . Data processing system comprising at least one microprocessor according to claim 1.