Method and system for error correction in flash memory
View Patent ↗A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
1. A controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the controller comprising:
an encoder adapted to receive a series of data bits and provide a series of encoded data bits;
a mapper adapted to convert the series of encoded data bits into a series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array; and
a demodulator adapted to generate an output signal based on the series of data symbols, the output signal characterized by a second number of digital levels greater than the first number of digital levels used to store the series of data symbols in the memory cell; and
a decoder adapted to output a series of output data symbols based on the output signal of the demodulator.
2. The controller of claim 1 wherein the encoder comprises a first encoder and the decoder comprises a first decoder, the controller further comprising:
a second encoder in communication with the first encoder; and
a second decoder in communication with the first decoder.
3. The controller of claim 2 wherein the first encoder is adapted to perform a first ECC technique and the second encoder is adapted to perform a second ECC technique.
4. The controller of claim 3 wherein the first ECC technique is different from the second ECC technique.
5. The controller of claim 1 wherein the multi-level solid state non-volatile memory array comprises one or more flash EEPROM arrays.
6. The controller of claim 1 wherein the series of output data symbols is generated based on soft information.
7. A method of operating a controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the method comprising:
encoding a first series of data bits to provide a series of encoded data bits;
converting the series of encoded data bits into a series of data symbols;
storing the series of data symbols in a memory cell of the multi-level solid state non-volatile memory array;
generating an output signal based on the series of data symbols, the output signal characterized by a second number of digital levels greater than the first number of digital levels used to store the series of data symbols in the memory cell; and
decoding the output signal to provide a series of output data symbols.
8. The method of claim 7 further comprising:
encoding of data bits to generate the first series of data bits; and
decoding the series of output data symbols.
9. The method of claim 8 wherein the encoding of the data bits is performed in accordance with a first ECC technique and the encoding of the first series of data bits is performed in accordance with a second ECC technique.
10. The method of claim 9 wherein the first ECC technique is different from the second ECC technique.
11. The method of claim 7 wherein the multi-level solid state non-volatile memory array comprises one or more flash EEPROM arrays.
12. The method of claim 7 further comprising processing soft information associated with the series of data symbols.
13. A controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the controller comprising:
means for encoding a first series of data bits to provide a series of encoded data bits;
means for converting the series of encoded data bits into a series of data symbols;
means for storing the series of data symbols in a memory cell of the multi-level solid state non-volatile memory array;
means for generating an output signal based on the series of data symbols, the output signal characterized by a second number of digital levels greater than the first number of digital levels used to store the series of data symbols in the memory cell; and
means for decoding the output signal to provide a series of output data symbols.
14. The controller of claim 13 further comprising:
means for encoding data bits to generate the first series of data bits; and
means for decoding the series of output data symbols.
15. The controller of claim 14 wherein the encoding of the data bits is performed in accordance with a first ECC technique and the encoding of the first series of data bits is performed in accordance with a second ECC technique.
16. The controller of claim 15 wherein the first ECC technique is different from the second ECC technique.
17. The controller of claim 13 wherein the multi-level solid state non-volatile memory array comprises one or more flash EEPROM arrays.
18. The controller of claim 13 further comprising means for processing soft information associated with the series of data symbols.