IP Library Granted Patent US 7,582,518
Granted Patent B2
US 7,582,518 · App. 11/598,817 · Granted Sep 1, 2009

High electron mobility transistor semiconductor device and fabrication method thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,582,518
App. No.
11/598,817
Granted
Sep 1, 2009
Kind
B2
Abstract

In a method of forming a semiconductor device on a semiconductor substrate ( 100 ), a photoresist layer ( 102 ) is deposited on the semiconductor substrate; a window ( 106 ) is formed in the photoresist layer ( 102 ) by electron beam lithography; a conformal layer ( 108 ) is deposited on the photoresist layer ( 102 ) and in the window ( 106 ); and substantially all of the conformal layer ( 108 ) is selectively removed from the photoresist layer ( 102 ) and a bottom portion of the window to form dielectric sidewalls ( 110 ) in the window ( 106 ).

Claims (48)

1. A method of forming a semiconductor device on a semiconductor substrate, the method comprising:

forming a photoresist layer on the semiconductor substrate;

forming a window in the photoresist layer;

forming a conformal layer comprised of a dielectric material on the photoresist layer and in the window;

selectively removing substantially all of the conformal layer from the photoresist layer and a bottom portion of the window to form dielectric sidewalls in the window,

depositing a metal film in the window;

isotropically etching the window to remove a portion of the conformal layer from the dielectric sidewalls of the window; and

lifting off the photoresist layer to form a metal gate from the metal film.

2. A method of forming a semiconductor device on a semiconductor substrate, the method comprising:

forming a photoresist layer on the semiconductor substrate;

forming a window in the photoresist layer;

forming a conformal layer comprised of a dielectric material on the photoresist layer and in the window; and

selectively removing substantially all of the conformal layer from the photoresist layer and a bottom portion of the window to form dielectric sidewalls in the window, wherein

the forming of the photoresist layer further includes forming a polymethyl methacrylate (PMMA) layer on the semiconductor substrate and forming a polymethyl methacrylate-methacrylic acid (PMMA-MAA) copolymer layer on the PMMA layer, and further wherein

the forming of the conformal layer further includes depositing the dielectric material at a temperature at which the PMMA layer and the PMMA-MAA copolymer layer do not flow.

3. A method of forming a semiconductor device on a semiconductor substrate, the method comprising:

forming a photoresist layer on the semiconductor substrate;

forming a window in the photoresist layer;

forming a conformal layer comprised of a dielectric material on the photoresist layer and in the window; and

selectively removing substantially all of the conformal layer from the photoresist layer and a bottom portion of the window to form dielectric sidewalls in the window, wherein

the forming of the window in the photoresist layer further includes forming the window by electron beam lithography (EBL).

4. The method of claim 3 , wherein

the dielectric material includes silicon nitride (SiN) and

the forming of the conformal layer includes depositing the SiN on the photoresist layer at a non-flowing temperature of the photoresist layer.

5. The method of claim 3 , wherein

the semiconductor substrate comprises an indium phosphide (InP) substrate.

6. The method of claim 3 , wherein

the selectively removing substantially all of the conformal layer from the photoresist layer and a bottom portion of the window to form dielectric sidewalls further includes applying an anisotropic inductive coupled plasma (ICP) etch to the conformal layer.

7. The method of claim 3 , wherein

the selectively removing substantially all of the conformal layer from the photoresist layer and a bottom portion of the window to form dielectric sidewalls further includes applying an anisotropic inductive coupled plasma (ICP) etch to the conformal layer at a radio frequency (RF) bias power between 10-50 W to control plasma energy and at an RF ICP power between 100-500 W to control ion generation.

8. The method of claim 3 , wherein

the selectively removing substantially all of the conformal layer from the photoresist layer and a bottom portion of the window to form dielectric sidewalls further includes directionally etching the photoresist layer and the window.

9. The method of claim 3 , further comprising:

depositing a metal film in the window and on the photoresist layer; and

lifting off the photoresist layer to form a metal T-gate from the metal film.

10. The method of claim 9 , wherein

the metal film comprises one of titanium, platinum and gold.

11. A method of forming a metal T-gate on a Group III-V semiconductor substrate, a polymethyl methacrylate (PMMA) layer deposited on the semiconductor substrate, a polymethyl methacrylate-methacrylic acid (PMMA-MAA) copolymer layer deposited on the PMMA layer, and a window formed in the PMMA-MAA copolymer layer and the PMMA layer, the method comprising:

depositing a dielectric layer on the PMMA-MAA copolymer layer and over the window;

selectively removing the dielectric layer to leave dielectric sidewalls in the window;

depositing a metal film in the window by evaporation; and

lifting off the PMMA layer and the PMMA-MAA copolymer layer to thereby form the metal T-gate from the metal film.

12. The method of claim 11 , wherein

the selectively removing of the dielectric layer to leave dielectric sidewalls in the window further includes applying an anisotropic inductive coupled plasma (ICP) etch to the dielectric layer.

13. The method of claim 11 , further including

prior to lifting off the PMMA layer and the copolymer layer, partially removing the dielectric layer from a portion of the PMMA layer by an isotropic reactive ion etch.

14. The method of claim 11 , wherein

the dielectric layer comprises silicon nitride (SiN).

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2010
From: NORTHROP GRUMMAN SPACE & MISSION SYSTEMS CORP.
To: NORTHROP GRUMMAN SYSTEMS CORPORATION
Reel/Frame 023915/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2009
From: NORTHROP GRUMMAN CORPORTION
To: NORTHROP GRUMMAN SPACE & MISSION SYSTEMS CORP.
Reel/Frame 023699/0551 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2007
From: NORTHROP GRUMMAN CORPORATION
To: NORTHROP GRUMMAN SPACE & MISSION SYSTEMS CORP.
Reel/Frame 018977/0782 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2006
From: DANG, LINH; YOSHIDA, WAYNE; MEI, XIAOBING; WANG, JENNIFER; LIU, PO-HSIN; LEE, JANE; LIU, WEIDONG; BARSKY, MICHAEL; LAI, RICHARD
To: NORTHROP GRUMMAN CORPORATION
Reel/Frame 018709/0479 →