IP Library Granted Patent US 9,177,111
Granted Patent B1
US 9,177,111 · App. 11/599,656 · Granted Nov 3, 2015

Systems and methods for protecting software

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Quick Facts
Patent No.
US 9,177,111
App. No.
11/599,656
Granted
Nov 3, 2015
Kind
B1
Abstract

A software protection system comprises a memory system and a microprocessing system. The memory system is configured to store a software program comprised of a plurality of program instructions that, when executed, have a program order. The microprocessing system is coupled to the memory system and is configured to, when executing the software program, determine a next program instruction of the plurality of program instructions in the program order based on an order identifier, fetch the next program instruction from the memory system, determine if the next program instruction requires decrypting, decrypt the next program instruction responsive to determining that the next program instruction requires decrypting, and execute the next program instruction.

Claims (38)

1. A software protection system comprising:

a memory system configured to store a software program comprised of a plurality of program instructions each comprising an opcode and an operand, wherein the plurality of program instructions, when executed, have a program order; and

a microprocessing system coupled to the memory system and configured to, when executing the software program, determine a next program instruction of the plurality of program instructions in the program order based on an order identifier, fetch the next program instruction from the memory system, compare the opcode of the next program instruction against a template comprising a group of unencrypted opcodes to determine if the next program instruction requires decrypting, decrypt the next program instruction responsive to determining that the next program instruction requires decrypting, and execute the next program instruction.

2. The software protection system of claim 1 wherein a first program instruction of the plurality of program instructions comprises an encryption flag indicating whether the software program is encrypted or unencrypted.

3. The software protection system of claim 2 wherein the microprocessing system is further configured to process the encryption flag of the first program instruction to determine if the next program instruction requires decrypting.

4. The software protection system of claim 1 wherein each of the opcodes of the plurality of program instructions include an encryption flag that indicates whether the associated program instruction is either encrypted or unencrypted.

5. The software protection system of claim 4 wherein the microprocessing system is further configured to process the encryption flag of the opcode of the next program instruction to determine if the next program instruction requires decrypting.

6. The software protection system of claim 1 wherein the next program instruction does not require decrypting if the opcode matches one of the group of unencrypted opcodes in the template.

7. The software protection system of claim 1 wherein the next program instruction requires decrypting if the opcode does not match one of the group of unencrypted opcodes in the template.

8. A method of operating a software protection system comprising:

storing in a memory system a software program comprised of a plurality of program instructions each comprising an opcode and an operand, wherein the plurality of program instructions, when executed, have a program sequence; and

when executing the software program in a microprocessing system:

determining in a microprocessing system a next program instruction of the plurality of program instructions in the program sequence based on a sequence identifier;

fetching the next program instruction from the memory system;

comparing the opcode of the next program instruction against a template comprising a group of unencrypted opcodes to determine if the next program instruction requires decrypting;

decrypting the next program instruction responsive to determining that the next program instruction requires decrypting; and

executing the next program instruction.

9. The method of claim 8 wherein a first program instruction of the plurality of program instructions comprises an encryption flag indicating whether the software program is encrypted or unencrypted.

10. The method of claim 9 , further comprising:

processing the encryption flag of the first program instruction to determine if the next program instruction requires decrypting.

11. The method of claim 8 wherein each of the opcodes of the plurality of program instructions include an encryption flag that indicates whether the associated program instruction is either encrypted or unencrypted.

12. The method of claim 11 , further comprising:

processing the encryption flag of the opcode of the next program instruction to determine if the next program instruction requires decrypting.

13. The method of claim 8 wherein the next program instruction does not require decrypting if the opcode matches one of the group of unencrypted opcodes in the template.

14. The method of claim 8 wherein the next program instruction requires decrypting if the opcode does not match one of the group of unencrypted opcodes in the template.

15. A microprocessing system for executing a software program comprised of a plurality of program instructions each comprising an opcode and an operand, wherein the plurality of program instructions, when executed, have a program order, the microprocessing system comprising:

an interface configured to read from a memory a first program instruction of the plurality of program instructions;

a processing system coupled to the interface and configured to

compare an opcode of the program instruction against a template comprising a group of unencrypted opcodes to determine if the program instruction requires decrypting, decrypt the program instruction responsive to determining that the program instruction requires decrypting, and execute the program instruction.

16. A method of operating a microprocessing system for executing a software program comprised of a plurality of program instructions each comprising an opcode and an operand, wherein the plurality of program instructions, when executed, have a program order, the method comprising:

reading a program instruction of the plurality of program instructions from a memory;

comparing an opcode of the program instruction against a template comprising a group of unencrypted opcodes to determine if the program instruction requires decrypting;

decrypting the program instruction responsive to determining that the program instruction requires decrypting; and

executing the program instruction.

17. The microprocessing system of claim 15 ,

wherein the program instruction does not require decrypting if the opcode matches one of the group of unencrypted opcodes in the template.

18. The method of operating a microprocessing system of claim 16 ,

wherein the program instruction requires decrypting if the opcode does not match one of the group of unencrypted opcodes in the template.

Assignments (8)
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040821/0550 →
CHANGE OF NAME Recorded Oct 25, 2012
From: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.
To: HGST NETHERLANDS B.V.
Reel/Frame 029341/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2010
From: PROMETHEAN STORAGE LLC
To: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.
Reel/Frame 025353/0179 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2006
From: SQUIRES, CHRISTOPHER J.; REH, JEFFREY G.
To: PROMETHEAN STORAGE LLC
Reel/Frame 018582/0086 →