Display device and manufacturing method thereof

1. A manufacturing method of a display device, comprising:

forming a plurality of gate wires comprising a gate electrode on an insulating substrate;

forming an electrode layer comprising a source electrode and a drain electrode spaced apart from each other to define a channel region on the gate electrode interposed therebetween;

forming a first barrier wall having a first opening for exposing the channel region, a portion of the source electrode, and a portion of the drain electrode on the electrode layer, the first barrier wall having a surface;

forming a shielding film to cover the channel region inside the first opening;

treating the surface of the first barrier wall;

removing the shielding film; and

forming an organic semiconductor layer inside the first opening.

2. The method according to claim 1 , wherein the electrode layer comprises a transparent conductive material.

3. The method according to claim 1 , wherein the forming of the shielding film comprises:

forming a shielding material layer;

light-exposing using a mask with an aperture of a predetermined pattern; and

developing the shielding material layer.

4. The method according to claim 1 , wherein the shielding film is formed through an ink jet method.

5. The method according to claim 4 , further comprising forming a passivation film on the organic semiconductor layer,

wherein at least one of the organic semiconductor layer and the passivation film is formed through an ink jet method.

6. The method according to claim 1 , wherein the surface treatment comprises at least one of an O 2 plasma treatment, a CF 4 plasma treatment, and a self-assembled monolayer (SAM) treatment.

7. The method according to claim 1 , further comprising forming a gate insulating film to cover the gate electrode before forming the electrode layer and after the plurality of gate wires have been formed, the electrode layer including at least one of ITO (Indium Tin Oxide), or IZO (Indium Zinc Oxide).

8. The method according to claim 7 , wherein the gate insulating film has a dielectric constant of between about 1 to about 3.

9. The method according to claim 1 , wherein the organic semiconductor layer comprises any one material selected from the group consisting of

a first derivative material consisting of tetracene or pentacene substituents,

oligothiophene with 4 to 8 thiophene rings coupled to one another through 2- and 5-positions of the thiophene rings,

one of perylenetetracarboxlic dianhidride (PTCDA) or an imide derivative thereof,

one of naphthalenetetracarboxlic dianhydride (NTCDA) or an imide derivative thereof,

one of metallized pthalocyanine or a halogenated derivative thereof,

one of perylene or coronene and one of a derivative including substituents thereof;

one of a co-oligmer or co-polymer of one of thienylene and vinylene,

thiophene,

one of thienylene or coronene and one of a derivative containing substituents thereof, and

a second derivative material including at least one hydrocarbon chain with 1 to 30 carbons in an aromatic or heteroaromatic ring of said second derivative material.

10. The method according to claim 1 , further comprising:

forming a plurality of data wires which are both insulated from and which cross the plurality of gate wires to define a pixel between the insulating substrate and the plurality of gate wires; and

forming an interlayer insulating film on the plurality of data wires.

11. The method according to claim 10 , wherein the interlayer insulating film comprises a lower first interlayer insulating film and an upper second interlayer insulating film, the first interlayer insulating film being made of an inorganic film comprising at least one of silicon nitride (SiNx) or silicon oxide (SiOx), the second interlayer insulating film being made of an organic film including an organic material.

12. The method according to claim 10 , wherein forming the interlayer insulating film comprises:

forming a second barrier wall with a second opening for exposing the gate electrode on the interlayer insulating film; and

forming the gate insulating film inside the second opening through an ink jet method.

13. The method according to claim 1 , wherein the passivation film comprises a lower first passivation film and an upper second passivation film, the first passivation film comprises a material selected from the group consisting of

cyclized transparent polymers obtained from a copolymerization of PTFE (Poly Tetra Fluro Ethylene),

FEP (Fluorinated Ethylene Propylene),

PFA (Poly Fluoro Alkoxy),

ETFE (Ethylene Tetra Fluoro Ethylene),

PVDF (Polyvinylidene Fluoride) or perfluoro (alkenylvinyl ethers),

the second passivation film comprising one of ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).