IP Library Patent Application 11603276
Patent Application
App. No. 11/603,276

Method of making a strained semiconductor device

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
11/603,276
Abstract

In a method of making a semiconductor device, a recess is formed in an upper surface of the semiconductor body of a first material. An embedded semiconductor region is formed in the recess. The embedded semiconductor region is formed from a second semiconductor material that is different than the first semiconductor material. An upper surface of the embedded semiconductor region is amorphized to create an amorphous region. A silicide is then formed over the amorphous region.

Claims (43)

1 . A method of making a semiconductor device, the method comprising:

providing a semiconductor body including an upper surface, the semiconductor body comprising a first semiconductor material;

creating a recess in the upper surface of the semiconductor body;

forming an embedded semiconductor region in the recess, the embedded semiconductor region comprising a second semiconductor material that is different than the first semiconductor material;

amorphizing an upper surface of the embedded semiconductor region to create an amorphous region; and

forming a silicide over the amorphous region.

2 . The method of claim 1 , wherein the first semiconductor material comprises silicon and the second semiconductor material comprises silicon germanium.

3 . The method of claim 2 , further comprising forming a silicon cap layer over the embedded semiconductor region before amorphizing the upper surface.

4 . The method of claim 3 , wherein amorphizing the upper surface is performed to a depth such that the amorphous region is located entirely within the silicon cap layer.

5 . The method of claim 2 , wherein forming the embedded semiconductor region comprises epitaxially growing silicon germanium using SiH 4 as a silicon source gas and GeH 4 as a germanium source gas.

6 . The method of claim 1 , wherein forming the embedded semiconductor region comprises selectively growing silicon as the second semiconductor material in the recess.

7 . The method of claim 1 , wherein amorphizing the upper surface comprises performing an implantation step.

8 . The method of claim 7 , wherein amorphizing the upper surface comprises implanting germanium ions into the embedded semiconductor region.

9 . The method of claim 7 , wherein amorphizing the upper surface comprises implanting xenon ions into the embedded semiconductor region.

10 . The method of claim 7 , wherein amorphizing the upper surface comprises implanting carbon ions into the embedded semiconductor region.

11 . The method of claim 1 , wherein forming the embedded semiconductor region comprises in situ doping of the embedded semiconductor region.

12 . The method of claim 1 , wherein forming a silicide comprises depositing a metal layer over the embedded semiconductor region and heating the region to form the silicide.

13 . The method of claim 12 , wherein the metal layer comprises a nickel layer.

14 . The method of claim 1 , wherein the first semiconductor material is silicon and the second semiconductor material is silicon carbon.

15 . A method of making a semiconductor device, the method comprising:

forming a recess in an upper surface of a silicon wafer;

growing an embedded silicon germanium region;

implanting a material to form an amorphous region over the silicon germanium region; and

forming a silicide over the amorphous region.

16 . The method of claim 15 , further comprising forming a silicon cap layer over the embedded silicon germanium region prior to implanting the material.

17 . The method of claim 16 , wherein the amorphous region is formed in the silicon cap layer.

18 . The method of claim 16 , wherein the amorphous region is formed entirely in the silicon cap layer.

19 . The method of claim 15 , wherein forming a silicide comprises depositing a metal layer over the embedded semiconductor region and heating the region to form the silicide.

20 . The method of claim 19 , wherein the metal layer comprises a nickel layer.

21 . A method of making a semiconductor device, the method comprising:

providing a semiconductor body including an upper surface, the semiconductor body comprising a first semiconductor material;

forming a gate electrode overlying the upper surface of the semiconductor body and insulated therefrom;

forming spacers adjacent to sidewalls of the gate electrode;

creating first and second recesses in the upper surface of the semiconductor body, the first recess being spaced from the second recess by the gate electrode;

forming embedded semiconductor source/drain regions in the first and second recesses, the embedded semiconductor source/drain regions each comprising a second semiconductor material that is different than the first semiconductor material;

amorphizing an upper surface of the embedded semiconductor source/drain regions to create an amorphous region; and

forming a silicide over the amorphous region.

22 . The method of claim 21 , wherein forming embedded semiconductor source/drain regions comprises forming p-doped embedded semiconductor source/drain regions.

23 . The method of claim 22 , wherein the first material is silicon and the second material is silicon germanium.

24 . The method of claim 23 , further comprising forming a silicon cap layer over the embedded semiconductor source/drain regions prior to amorphizing the upper surface.

25 . The method of claim 23 , wherein forming a silicide comprises forming nickel silicide.

26 . The method of claim 21 , further comprising forming a stress-inducing layer over the upper surface after forming the silicide.

27 . The method of claim 21 , wherein making a semiconductor device comprises making a field effect transistor with a channel length that is less than 65 nm.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2007
From: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
To: INFINEON TECHNOLOGIES AG
Reel/Frame 019168/0507 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2007
From: KWON, OH-JUNG; UTOMO, HENRY
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019158/0314 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2007
From: KWON, O SUNG; HAN, JIN-PING
To: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Reel/Frame 019158/0360 →