Circuit arrangement for reducing a crest factor, and method for reducing a signal dynamic range
View Patent ↗To reduce the crest factor of a total signal, the signal dynamic range is corrected in baseband upstream of the interpolation filters. To this end, provision is made for the input of a correction device to be coupled to at least two signal sources which are designed to provide digital signals on different frequency bands. The correction device is designed to determine correction factors from the digital signals applied to the input and use them to alter the respective digital signals. The output of the correction device is coupled to a first and at least one second interpolation filter. This allows reduction of the signal dynamic range in baseband, which reduces the crest factor without having to accept substantial losses in signal quality.
1. A method for reducing a signal dynamic range, comprising:
producing a first digital signal on a first carrier frequency, and at least one second digital signal on a second carrier frequency using first and second clock signals, respectively, the first and second clock signals having a respective clock frequency;
evaluating an amplitude component of the first and second digital signals by forecasting an impulse response from each of a first filter and a second filter, respectively, for different instants within a clock period of the respective clock frequency;
ascertaining a correction factor by comparing the evaluated amplitude components with a threshold value;
selectively altering at least one signal from the set of the first and at least one second signal with the correction factor;
filtering the at least one altered signal of the first and the at least one second digital signal with a respective one of the first filter and the second filter; and
adding the filtered signals to form a total signal.
2. The method of claim 1 , wherein evaluating an amplitude component comprises:
producing a plurality of forecast signals that respectively represent an output value which is brought about at different instants within a clock period of the respective clock frequency by a forecast impulse response of the filter;
combining the forecast signals produced from the first and the at least one second digital signal to form a total forecast signal such that the output values respectively produced for the same instant within a clock period of the respective clock frequency are combined.
3. The method of claim 2 , wherein the number of forecast signals for each signal corresponds at least to four times the number of the first and the at least one second signal.
4. The method of claim 1 , wherein the filtering comprises interpolating the at least one altered signal or the first and the at least one second digital signal.
5. A circuit arrangement for reducing the crest factor, comprising:
a first signal generator configured to produce a first digital signal with a clock period, the first digital signal having an amplitude component;
a second signal generator configured to produce a second digital signal, the second digital signal having an amplitude component;
a correction device whose input is connected to the first and the second signal generator and which has a first and a second output;
a first shaping filter for interpolation, connected to the first output of the correction device;
a second shaping filter for interpolation, connected to the second output of the correction device; and
a summation component connected to the first and the second shaping filter, and configured to add together the digital signals which are output by the first and the second shaping filter;
wherein the correction device comprises:
a first forecast device configured to receive the first digital signal and generate a first forecast output reflecting a forecast impulse response of the first shaping filter comprising a plurality of first signal elements, wherein each of the plurality of first signal elements is associated with a respective one of a plurality of different phases associated with the clock period;
a second forecast device configured to receive the second digital signal and generate a second forecast output reflecting a forecast impulse response of the second shaping filter comprising a plurality of second signal elements, wherein each of the second signal elements is associated with a respective one of the plurality of different phases associated with the clock period;
an adder component configured to sum respective first and second signal elements of a given phase for each of the plurality of different phases, thereby generating a plurality of total forecast signals associated with the plurality of different phases; and
a correction value generator configured to receive the plurality of total forecast signals and generate correction values based on the plurality of total forecast signals.
6. The circuit arrangement of claim 5 , further comprising:
a first and second plurality of mixing devices associated with each of the first and second forecast devices, wherein each of the plurality of first and second mixing devices is associated with a respective one of the plurality of different phases associated with the clock period; and
first and second numerically controlled oscillators coupled to each of the first and second plurality of mixing devices of the first and second forecast devices, respectively,
wherein the first mixing devices are configured to multiply a first plurality of digital oscillator signals from the first numerically controlled oscillator with respective ones of the plurality of first signal elements to generate frequency shifted first signal elements, and
wherein the second mixing devices are configured to multiply a second plurality of digital oscillator signals from the second numerically controlled oscillator with respective ones of the plurality of second signal elements to generate frequency shifted second signal elements.
7. The circuit arrangement of claim 6 , wherein the first and second numerically controlled oscillators are configured to generate a first and second plurality of digital oscillator signals associated with different frequencies.
8. The circuit arrangement of claim 6 , wherein the adder component is configured to sum respective first and second frequency shifted elements of a given phase for each of the plurality of different phases to thereby generate the plurality of total forecast signals.
9. The circuit arrangement of claim 5 , wherein each of the first and second forecast devices comprise a plurality of filters, wherein each of the plurality of filters is associated with a respective one of the plurality of different phases, and wherein an output of each of the plurality of filters provides collectively the plurality of first and second signal elements, respectively.
10. The circuit arrangement of claim 5 , wherein each of the first and second forecast devices comprise:
a first number of filters configured to generate a forecast; and
a first number of sample and hold circuits configured to repeat the forecast from a respective filter a predetermined number of times, wherein the first number multiplied by the predetermined number corresponds to the plurality of different phases of the clock period.
11. The circuit arrangement of claim 5 , wherein the correction value generator is configured to produce an error signal from a comparison between each of the plurality of total forecast signals and a threshold value, thereby resulting in a plurality of error signals.
12. The circuit arrangement of claim 11 , wherein each error signal is dependent on the threshold value when the threshold value is exceeded.
13. The circuit arrangement of claim 11 , wherein the correction value generator is further configured to generate the correction values based on the plurality of error signals.
14. The circuit arrangement of claim 11 , wherein the correction value generator further comprises one or more weighting factors for each of the plurality of error signals, and wherein the correction value generator is configured to generate the correction values based on the plurality of weighted error signals.