Multi-port semiconductor memory
View Patent ↗A multi-port semiconductor memory in which wrong read-out due to coupling noise is hardly generated and operation speed is fast is provided. When data are written in memory cells from a pair of bit lines for one port, NMOS transistors become on. Electrical potential only at a low-level side is pulled up between the pair of bit lines, because electrical potential at a high-level side is approximately equivalent to power potential. Accordingly, when one of adjacent bit lines is on high-level and the other is on low-level, potential difference is reduced by the pull-up, resulting in reduction of generating time of the coupling noise. Although read-out of data can not be performed while the coupling noise is being generated, since the concerned generating time is reduced in the invention, the operation speed is substantially fast.
1. A semiconductor memory comprising:
a memory cell array including a plurality of memory cells,
a first bit line pair connected to the plurality of memory cells and performing write-in or read-out of complementary data for the plurality of memory cells in the memory cell array,
a second bit line pair performing write-in or read-out of complementary data for the plurality of memory cells in the memory cell array,
a plurality of first word lines provided to the plurality of memory cells for selecting a first memory cell from the memory cell array,
a plurality of second word lines provided to the plurality of memory cells for selecting a second memory cell from the memory cell array,
a first pull-up circuit that, when data is written in the first memory cell from the first bit line pair, pulls up low level of a lower-level line of the first bit line pair, and
a plurality of first regulator circuits each connected to a corresponding one of the plurality of memory cells,
wherein the first regulator circuit places the first memory cell in a floating state when the first memory cell is selected, and connects the first memory cell to a predetermined voltage when the first memory cell is not selected.
2. A semiconductor memory according to claim 1 , further comprising:
a second pull-up circuit that, when data is written in the first memory cell that is selected from the second bit line pair, pulls up low level of a lower-level line of the second bit line pair.
3. A semiconductor memory according to claim 1 ,
wherein the first regulator circuit includes a MOS transistor, the MOS transistor being connected to the first memory cell and a line with which a predetermined voltage is provided, and
wherein the MOS transistor is turned off when data is written in the first memory cell from the first bit line pair.
4. A semiconductor memory according to claim 1 , wherein a source and a drain of the MOS transistor of the first regulator circuit are connected to a ground and a source of the MOS transistor of the first memory cell, respectively.