Granted Patent B2

US 7,626,215 · App. 11/604,694 · Granted Dec 1, 2009

Abstract

Claims (46)

1. A semiconductor device, comprising:

a silicon substrate;

a gate insulating film formed on said silicon substrate;

a gate electrode formed on said gate insulating film;

two first conductivity type impurity diffused layers formed in a surface of said silicon substrate, said impurity diffused layers sandwiching said gate electrode in a plan view and each having a trench formed in a surface thereof; and

two first conductivity type semiconductor layers each epitaxially grown from a bottom of the trench, wherein

a conductivity type of a region of said silicon substrate immediately below said gate insulating film is a second conductivity type, and

each of said first conductivity type semiconductor layers comprises:

a first region including a portion located within or lower than a same plane with an interface between said silicon substrate and said gate insulating film; and

a second region located closer to a bottom side of the trench than said first region, said second region having a first lattice constant closer to a second lattice constant of silicon than a third lattice constant of said first region;

wherein an upper surface of said first region is located higher than the same plane with the interface between said silicon substrate and said gate insulating film,

wherein a lower surface of said first region is located lower than the same plane with the interface between said silicon substrate and said gate insulating film,

wherein said second region is lattice-matched to said silicon substrate, and

wherein said first region is lattice-matched to said second region.

2. The semiconductor device according to claim 1 , wherein the third lattice constant of said first conductivity type first region is maximum inside said semiconductor layers.

3. The semiconductor device according to claim 2 , wherein

said second region is constituted of silicon germanium having a germanium concentration which increases with distance from the bottom of the trench, and

said first region is constituted of silicon germanium having a germanium concentration that corresponds to the germanium concentration at an uppermost surface of said second region.

4. The semiconductor device according to claim 2 , wherein

a germanium concentration in said first region is 20 atom % or higher, and

a germanium concentration in said second region is lower than 20 atom %.

5. The semiconductor device according to claim 1 , wherein

each of said first conductivity type semiconductor layers comprises a third region located higher than said first region, said third region having a fourth lattice constant closer to the second lattice constant of silicon than the third lattice constant of said first region, and

a silicide layer is formed on said third region.

6. The semiconductor device according to claim 5 , wherein said third region is constituted of silicon or silicon germanium having a germanium concentration lower than 20 atom %.

7. The semiconductor device according to claim 1 , wherein a side surface of the trench is a <111> plane.

8. The semiconductor device according to claim 1 , wherein

the first conductivity type is p-type, the second conductivity type is n-type, and each of said semiconductor layers include a silicon germanium layer.

9. The semiconductor device according to claim 1 , wherein

the first conductivity type is n-type, the second conductivity type is p-type, and each of said semiconductor layers include a silicon layer in which carbon is introduced.

10. A semiconductor device, comprising:

a silicon substrate;

a gate insulating film formed on said silicon substrate;

a gate electrode formed on said gate insulating film;

two first conductivity type impurity diffused layers formed in a surface of said silicon substrate, said impurity diffused layers sandwiching said gate electrode in a plan view and each having a trench formed in a surface thereof;

two first conductivity type semiconductor layers each epitaxially grown from a bottom of the trench; and

a silicide layer formed on each of said semiconductor layers, wherein

a conductivity type of a region of said silicon substrate immediately below said gate insulating film is a second conductivity type, and

each of said first conductivity type semiconductor layers comprise:

a fourth region including a portion located within or lower than a same plane with an interface between said silicon substrate and said gate insulating film; and

a fifth region in contact with said silicide layer, said fifth region having a fifth lattice constant closer to a sixth lattice constant of silicon than a seventh lattice constant of said fourth region;

wherein an upper surface of said fourth region is located higher than the same plane with the interface between said silicon substrate and said gate insulating film, and

wherein a lower surface of said fourth region is located lower than the same plane with the interface between said silicon substrate and said gate insulating film, and

wherein said fifth region is lattice-matched to said fourth region.

11. The semiconductor device according to claim 10 , wherein the seventh lattice constant of said first conductivity type fourth region is maximum inside said semiconductor layers.

12. The semiconductor device according to claim 10 , wherein said fourth region is constituted of silicon germanium having a germanium concentration of 20 atom % or higher, and said first conductivity type fifth region is constituted of silicon or silicon germanium having a germanium concentration lower than 20 atom %.

Assignments (6)