Complex number multiplier
View Patent ↗The invention concerns a complex number multiplier receiving the binary number A, B, C and D complimentarily coded in pairs so as to perform the complex multiplication (A+jB)*(C+jD). A first processing stage enables to perform the operations A−B, C−D, and A+B whereof the results are binary numbers in base two with a redundant binary format, and a borrow-save coding for subtractions and carry-save coding for addition. A second processing stage converts said results into coded binary numbers in base four. A third processing stage enables to perform multiplication (A−B)C, (C−D)B and (A+B)D with a redundant binary format and a borrow-save coding. A last stage comprises two adders for working out the real part (A−B)C+(C−D)B and the imaginary part (A+B)D+(C−D)B in a redundant binary format and a borrow-save coding.
1. A complex number multiplier, comprising:
an input for receiving a real part A and an imaginary part B of a first complex number, and a real part C and an imaginary part D of a second complex number, wherein A, B, C, D are binary numbers coded in two's complement;
a first processing stage comprising a subtractor module configured to perform operations A−B and C−D, wherein results of each subtraction are a base two binary number with a redundant binary format and a borrow-save coding, and an adder module configured to perform operation A+B, wherein a result of this addition is a base two binary number with a redundant format and a carry-save coding;
a second processing stage comprising a converter configured to convert numbers delivered by the first processing stage into base four coded binary numbers with a redundant format;
a third processing stage comprising a multiplier configured to perform operations (A−B) C, (C−D)B and (A+B) D, wherein results of these operations are base two coded numbers with a redundant format; and
a fourth processing stage comprising two adders configured to compute a real part and an imaginary part of a product of two input complex numbers from numbers delivered by the third processing stage, wherein the real and imaginary parts are to the base two according to a redundant binary format.
2. The complex number multiplier of claim 1 , wherein the adders incorporate a borrow-save coding binary tree.
3. The complex number multiplier of claim 1 , wherein the multiplier comprises three distinct real multipliers configured to perform operations (A−B)C, (C−D)B and (A+B)D respectively, and wherein each multiplier comprises internal means configured to perform an addition of two partial products X and Y by perform operation X− Y −1, where Y denotes the 1's complement of Y.
4. The complex number multiplier of claim 3 , wherein the real multipliers and adders incorporate a borrow-save coding binary tree.
5. The complex number multiplier of claim 3 , wherein the internal means of the real multipliers comprise an inverter for delivering the number Y and a means of wiring for performing operation X− Y .
6. The complex number multiplier of claim 5 , wherein the real multipliers and adders incorporate a borrow-save coding binary tree.
7. The complex number multiplier of claim 1 , wherein the subtractor module comprises two distinct modules configured to perform operations A−B and C−D, and wherein the subtractor module and the adder module are embodied solely by wiring.
8. The complex number multiplier of claim 7 , wherein the multiplier comprises three distinct real multipliers configured to perform operations (A−B)C, (C−D)B and (A+B)D respectively, and wherein each multiplier comprises internal means configured to perform an addition to two partial products X and Y by performing operation X− Y −1, where Y denotes the 1's complement of Y.
9. The complex number multiplier of claim 8 , wherein the real multipliers and adders incorporate a borrow-save coding binary tree.
10. The complex number multiplier of claim 8 , wherein the internal means of the real multipliers comprise an inverter for delivering the number Y and a means of wiring for performing operation X− Y .
11. The complex number multiplier of claim 10 , wherein the real multipliers and adders incorporate a borrow-save coding binary tree.
12. A complex number multiplier, comprising:
an input for receiving a real part A and an imaginary part B of a first complex number, and a real part C and an imaginary part D of a second complex number, wherein A, B, C, D are binary numbers coded in two's complement form;
a first processing stage which outputs values representing operations A−B, C−D, and A+B, wherein the A−B and C−D values are each a base two binary number with a redundant binary format and a borrow - save coding, wherein the A+B value is a base two binary number with a redundant format and a carry - save coding;
a second processing stage comprising a converter configured to convert numbers delivered by the first processing stage into base four coded binary numbers with a redundant format;
a third processing stage comprising one or more multipliers configured to perform operations ( A−B ) C, ( C−D ) B and ( A+B ) D, wherein results of these operations are base two coded numbers with a redundant format; and
a fourth processing stage comprising two adders configured to compute a real part and an imaginary part of a product of two input complex numbers from numbers delivered by the third processing stage, wherein the real and imaginary parts are base two with a redundant binary format.
13. The complex number multiplier as recited in claim 12 wherein the A−B value output by the first processing stage comprises an arrangement of bits from A and B, and wherein the C−D value output by the first processing stage comprises an arrangement of bits from C and D, and wherein the A+B value comprises another arrangement of bits from A and B.
14. The complex number multiplier as recited in claim 13 wherein the A−B value comprises pairing of respective bits from respective bit positions of A and B, and wherein the C−D value comprising pairing of respective bits from respective bit positions of C and D.
15. The complex number multiplier as recited in claim 14 wherein the values A−B and C−D are formed in the first processing stage solely by wiring.
16. The complex number multiplier as recited in claim 14 wherein the pairing of respective bits is provided in a first order for a most significant bit position of A and B, and wherein the pairing of respective bits is provided in a second order for each other bit position of A and B.
17. The complex number multiplier as recited in claim 16 wherein the first order comprises the most significant bit of B followed by the most significant bit of A.
18. The complex number multiplier as recited in claim 17 wherein the second order comprises the respective bit of A followed by the respective bit of B.
19. The complex number multiplier as recited in claim 12 where the values A−B, C−D, and A+B are formed in the first processing stage solely by wiring.
20. The complex number multiplier as recited in claim 12 wherein the adders in the fourth processing stage comprise a borrow- save coding tree.
21. The complex number multiplier as recited in claim 12 wherein the one or more multipliers in the third processing stage comprises a borrow- save coding tree.
22. A mobile phone comprising a complex number multiplier comprising:
an input for receiving a real part A and an imaginary part B of a first complex number, and a real part C and an imaginary part D of a second complex number, wherein A, B, C, D are binary numbers coded in two's complement form;
a first processing stage which outputs values representing operations A−B, A+B, and C−D, wherein the A−B and C−D values are each a base two binary number with a redundant binary format and a borrow - save coding, wherein the A+B value is a base two binary number with a redundant format and a carry - save coding;
a second processing stage comprising a converter configured to convert numbers delivered by the first processing stage into base four coded binary numbers with a redundant format;
a third processing stage comprising one or more multipliers configured to perform operations ( A−B ) C, ( C−D ) B and ( A+B ) D, wherein results of these operations are base two coded numbers with a redundant format; and
a fourth processing stage comprising two adders configured to compute a real part and an imaginary part of a product of two input complex numbers from numbers delivered by the third processing stage, wherein the real and imaginary parts are base two with a redundant binary format.
23. The mobile phone as recited in claim 22 wherein the A−B value output by the first processing stage comprises an arrangement of bits from A and B, and wherein the C−D value output by the first processing stage comprises an arrangement of bits from C and D, and wherein the A+B value output by the first processing stage comprises another arrangement of bits from A and B.
24. The mobile phone as recited in claim 23 wherein the A−B value comprises pairing of respective bits from respective bit positions of A and B, and wherein the C−D value comprises pairing of respective bits from respective bit positions of C and D.
25. The mobile phone as recited in claim 24 wherein the values A−B and C−D are formed in the first processing stage solely by wiring.
26. The mobile phone as recited in claim 22 wherein the values A+B, A−B, and C−D are formed in the first processing stage solely by wiring.
27. The mobile phone as recited in claim 22 wherein the adders in the fourth processing stage comprise a borrow- save coding tree.
28. The mobile phone as recited in claim 22 wherein the one or more multipliers in the third processing stage comprise a borrow- save coding tree.