Semiconductor device
View Patent ↗A memory voltage monitoring circuit generates a low voltage detection signal when a power supply voltage drops below a memory contents holding voltage. A reset circuit generates a reset signal from an external reset signal and outputs the reset signal to the memory voltage monitoring circuit as an operation permission/no-permission signal. The memory voltage monitoring circuit operates while the reset signal shows operation permission.
1. A semiconductor device comprising:
a memory voltage monitoring circuit generating a low voltage detection signal when a power supply voltage drops below a memory contents holding voltage; and
a reset circuit generating a reset signal from an external reset signal, the external reset signal being generated by an operation voltage monitoring circuit when the power supply voltage drops below an operation voltage of the semiconductor device, and outputting the reset signal to the memory voltage monitoring circuit as an operation permission/no-permission signal, wherein
the memory voltage monitoring circuit operates while the reset signal shows operation permission.
2. The semiconductor device according to claim 1 , further comprising a low voltage detection signal holding circuit holding the low voltage detection signal.
3. The semiconductor device according to claim 2 , wherein
the reset circuit generates the reset signal showing the operation permission while the external reset signal shows that the power supply voltage is below the operation voltage.
4. The semiconductor device according to claim 3 , further comprising an internal circuit that monitors whether the low voltage detection signal holding circuit holds the low voltage detection signal or not while the reset signal shows the operation permission, wherein
the internal circuit outputs a clear signal when it detects that the low voltage detection signal holding circuit holds the low voltage detection signal, and
the low voltage detection signal holding circuit stops holding the low voltage detection signal when it detects the clear signal.
5. The semiconductor device according to 3 , wherein
the operation voltage and the memory contents holding voltage have a relation such that the operation voltage > the memory contents holding voltage.
6. The semiconductor device according to claim 1 , wherein
the low voltage detection signal is a signal showing that the data stored in the semiconductor device is defective in reliability.
7. The semiconductor device according to claim 1 , further comprising an OR circuit, wherein
the reset circuit outputs the reset signal to the OR circuit instead of outputting it to the memory voltage monitoring circuit, and
the OR circuit generates an OR signal between an operation control signal set by a program and the reset signal and outputs the OR signal to the memory voltage monitoring circuit as the operation permission/no-permission signal.
8. The semiconductor device according to claim 1 , further comprising a synchronous circuit cell, wherein
the reset circuit outputs the reset signal to the synchronous circuit cell instead of outputting it to the memory voltage monitoring circuit, and
the synchronous circuit cell controls an operation control signal set by a program based on the reset signal and outputs it to the memory voltage monitoring circuit as the operation permission/no-permission signal.