Integrated circuit chip with external pads and process for fabricating such a chip
View Patent ↗An integrated circuit chip has a dielectric surface layer and, below this layer, internal pads. The chip is fabricated by producing multiplicities of vias made of an electrically conducting material which pass through said surface layer and are positioned respectively above the internal pads. Projecting external contact pads are formed on the surface layer and connected respectively to the multiplicities of vias.
1. An integrated circuit chip, comprising:
a top-most circuit layer;
one or more internal pads formed on a top surface of the top-most circuit layer;
a conformal dielectric passivation layer covering the internal pads and top-most circuit layer;
multiplicities of vias made of an electrically conducting material passing through said conformal dielectric passivation layer and made respectively above each of said internal pads; and
one or more external contact pads formed on a top surface of said conformal dielectric passivation layer over and connected respectively to said multiplicities of vias, wherein the external contact pads project above the top surface of said conformal dielectric passivation layer such that sides of the external contact pads are exposed.
2. The chip according to claim 1 , wherein said multiplicities of vias are provided beneath flat front faces of bumps formed by the conformal dielectric passivation layer over each internal pad and wherein said projecting external contact pads are formed on top of these flat front faces.
3. The chip according to claim 1 , wherein said external contact pads have flat front faces on top surfaces thereof.
4. The chip according to claim 1 , wherein said internal pads are made of aluminum, said vias are made of tungsten and said external contact pads are made of gold.
5. An integrated circuit chip, comprising:
a top-most circuit layer;
an internal metal pad on a top surface of the top-most circuit layer;
a conformal dielectric layer covering the internal metal pad and top-most circuit layer, the dielectric layer including a bump region at a location of the internal metal pad;
at least one electrical via formed in the conformal dielectric layer through the bump region; and
a parallelepipedal shaped external contact pad upwardly extending from a top surface of the conformal dielectric layer at the location of the bump region and in electrical contact with the at least one via, wherein sides of the external contact pad are exposed above the top surface of the conformal dielectric layer.
6. The chip of claim 5 wherein the external contact pad has a substantially flat top surface.
7. The chip of claim 5 wherein the at least one electrical via comprises a multiplicity of electrical vias arranged in matrix format.
8. The chip of claim 5 , wherein the internal metal pad is made of aluminum, the via is made of tungsten and the external contact pad is made of gold.
9. An integrated circuit chip, comprising:
an internal metal pad formed on a top surface of a integrated circuit;
a conformal dielectric layer covering the internal metal pad and top surface, the dielectric layer including a bump region at a location of the internal metal pad;
at least one electrical via formed in the conformal dielectric layer through the bump region; and
an external contact pad formed on a top surface of the conformal dielectric layer at the location of the bump region and in electrical contact with the at least one via, the external contact pad projecting above the top surface of the conformal dielectric layer and having exposed sides.
10. The chip of claim 9 wherein the external contact pad has a substantially flat top surface.
11. The chip of claim 9 wherein the at least one electrical via comprises a multiplicity of electrical vias arranged in matrix format.
12. The chip of claim 9 , wherein the internal metal pad is made of aluminum, the via is made of tungsten and the external contact pad is made of gold.
13. An integrated circuit chip, comprising:
an internal pad formed on a top surface of an integrated circuit;
a dielectric passivation layer covering the internal pad and top surface of the integrated circuit;
vias made of an electrically conducting material passing through said dielectric passivation layer above said internal pad; and
an external contact pad formed on a top surface of said dielectric passivation layer over and connected to said vias, the external contact pad projecting above the top surface of said dielectric passivation layer so as to expose sides of the external contact pad.
14. The chip according to claim 13 , wherein said vias are provided beneath a flat front face of a conformal bump formed by the dielectric passivation layer over the internal pad and wherein said projecting external contact pad is formed on top of the flat front face.
15. The chip according to claim 13 , wherein said external contact pad has a flat front face on a top surface thereof.
16. The chip according to claim 13 , wherein said internal pad is made of aluminum, said vias are made of tungsten and said external contact pad is made of gold.