IP Library Granted Patent US 8,253,856
Granted Patent B1
US 8,253,856 · App. 11/608,968 · Granted Aug 28, 2012

Method and/or architecture for interlaced video resampling and color format conversion using combined vertical-temporal resolution extensions

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Quick Facts
Patent No.
US 8,253,856
App. No.
11/608,968
Granted
Aug 28, 2012
Kind
B1
Abstract

An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to a first interlaced video signal. The second circuit may be configured to generate a second interlaced video signal in response to the first interlaced video signal, the first control signal, the second control signal and the third control signal. The second circuit may be further configured to vertically scale the first interlaced video signal in an extended vertical domain.

Claims (44)

1. An apparatus comprising:

a first circuit configured to generate a first control signal, a second control signal and a third control signal in an interlace domain in response to spatial and motion contents of a first interlaced video signal; and

a second circuit configured to generate a second interlaced video signal in the interlace domain according to said first interlaced video signal, said first, second and third control signals, wherein said first, second and third control signals are used in an adaptive phase control and a color format control within said second circuit to further control interpolation and vertical scaling of said first interlaced video signal in an extended vertical domain, and this vertical scaling is associated with operation in an intermediate progressive domain to extend interlace spectrum and reduce aliasing artifacts.

2. The apparatus according to claim 1 , wherein said first and said second circuit comprise an integrated vertical-temporal adaptive scaler and color format converter.

3. The apparatus according to claim 1 , further comprising a horizontal scaler configured to generated said first interlaced video signal in response to an interlaced video input signal.

4. The apparatus according to claim 1 , wherein said first circuit comprises:

a frame/field 2D spatial detector configured to generate said first control signal in response to said first interlaced video signal; and

a frame/field motion detector configured to generate said second control signal and said third control signal in response to said first interlaced video signal.

5. The apparatus according to claim 4 , wherein said second circuit comprises:

an adaptive phase control configured to generate a fourth control signal in response to said first control signal and said second control signal;

a color format control configured to generate a fifth control signal in response to said third control signal;

a first 2D interpolator/vertical scaler configured to generate a first intermediate signal in response to said first control signal, said second control signal, said fourth control signal, said first interlaced video signal and a scaling factor;

a second 2D interpolator/vertical scaler configured to generate a second intermediate signal in response to said first control signal, said second control signal, said fourth control signal, said fifth control signal, said first interlaced video signal and said scaling factor; and

a vertical decimator configured to generate said second interlaced video signal in response to said first intermediate signal and said second intermediate signal.

6. The apparatus according to claim 5 , wherein:

said first 2D interpolator/vertical scaler is configured to process luminance information; and

said second 2D interpolator/vertical scaler is configured to process chrominance information.

7. The apparatus according to claim 6 , wherein said second 2D interpolator/vertical scaler is further configured to perform color format conversion.

8. The apparatus according to claim 7 , wherein said color format control is configured to determine a phase offset for top and bottom fields for compliance with the various color format standards.

9. The apparatus according to claim 5 , wherein said adaptive phase control is configured to control a phase of the first 2D interpolator/vertical scaler and a phase of the second 2D interpolator/vertical scaler according to a spatial detection signal generated by a frame/field 2D spatial detector and a temporal detection signal generated by a frame/field motion detector.

10. The apparatus according to claim 5 , wherein:

said frame/field 2D spatial detector and said frame/field motion detector operate in a first interlace domain;

said adaptive phase control, said first 2D interpolator/vertical scaler, said second 2D interpolator/vertical scaler and said color format control operate in said first interlaced domain and a progressive domain; and

said vertical decimator operates in a second interlace domain.

11. The apparatus according to claim 1 , wherein said first circuit and said second circuit are used to perform an interlaced-to-progressive conversion.

12. A method of interlaced video resampling and color format conversion comprising the steps of:

generating a first control signal, a second control signal and a third control signal in an interlace domain in response to spatial and motion contents of a first interlaced video signal; and

generating a second interlaced video signal in the interlace domain according to said first interlaced video signal, said first, and third control signals, wherein said first, second and third control signals are used in an adaptive phase control and a color format control to further control interpolation and vertical scaling of said first interlaced video signal in an extended vertical domain, and this vertical scaling is associated with operation in an intermediate progressive domain to extend interlace spectrum and reduce aliasing artifacts.

13. The method according to claim 12 , wherein said first control signal comprises a spatial detection signal, said second control signal comprises a temporal detection signal and said third control signal comprises a top/bottom field signal.

14. The method according to claim 13 , wherein generating the second interlaced video signal further comprises:

generating a phase control signal in response to said spatial detection signal and said temporal detection signal; and

generating a color format control signal in response to said top/bottom field signal.

15. The method according to claim 14 , wherein generating the second interlaced video signal further comprises:

generating a first intermediate signal by performing 2D interpolation and vertical scaling on a luminance component of said first interlaced video signal using said phase control signal, said spatial detection signal, said temporal detection signal and a scaling factor signal.

16. The method according to claim 15 , wherein generating the second interlaced video signal further comprises:

generating a second intermediate signal by performing 2D interpolation and vertical scaling on a chrominance component of said first interlaced video signal using said phase control signal, said spatial detection signal, said temporal detection signal, said color format control signal and said scaling factor signal.

17. The method according to claim 16 , wherein generating the second interlaced video signal further comprises vertically decimating the first intermediate signal and the second intermediate signal.

18. The method according to claim 17 , wherein:

said first interlaced video signal, said spatial detection signal, said temporal detection signal, and said top/bottom field signal are generated in a first interlace domain; and

said first intermediate signal and said second intermediate signal are generated in a progressive domain and vertically decimated in a second interlace domain.

19. The method according to claim 12 , further comprising the step of generating said first interlaced video signal by horizontally scaling an interlaced video input signal.

20. An apparatus comprising:

means for generating an intermediate signal by horizontally scaling a first interlaced video signal in an interlace domain; and

means for generating a second interlaced video signal in the interlace domain in response to said intermediate signal, wherein said second interlaced video signal generating means is further configured to interpolate and vertically scale said intermediate signal in an extended vertical domain, and this vertical scaling is associated with operation in an intermediate progressive domain based on an adaptive phase control and a color format control that are determined in the interlace domain by spatial and motion contents of the intermediate signal.

Assignments (12)
RELEASE OF SECURITY INTEREST Recorded Mar 4, 2023
From: EAST WEST BANK
To: GEO SEMICONDUCTOR INC.
Reel/Frame 062955/0700 →
SECURITY INTEREST Recorded Jul 26, 2022
From: GEO SEMICONDUCTOR INC.
To: EAST WEST BANK
Reel/Frame 060925/0979 →
RELEASE OF SECURITY INTEREST Recorded Jul 23, 2022
From: CRESCENT COVE CAPITAL II, LP
To: GEO SEMICONDUCTOR, INC.
Reel/Frame 060840/0079 →
SECURITY INTEREST Recorded May 31, 2019
From: GEO SEMICONDUCTOR INC.
To: CRESCENT COVE CAPITAL II, LP
Reel/Frame 049337/0040 →
RELEASE OF SECURITY INTEREST Recorded May 31, 2019
From: SCOTT LAKE HOLDINGS INC.
To: GEO SEMICONDUCTOR INC.
Reel/Frame 050340/0516 →
RELEASE OF SECURITY INTEREST Recorded May 31, 2019
From: ROADMAP GEO LP III
To: GEO SEMICONDUCTOR INC.
Reel/Frame 049334/0793 →
RELEASE OF SECURITY INTEREST Recorded May 24, 2019
From: BISHOPSGATE HOLDINGS CORPORATION
To: GEO SEMICONDUCTOR INC.
Reel/Frame 049286/0365 →
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NO. FROM US12027189 TO PCTUS1227189 PREVIOUSLY RECORDED ON REEL 044958 FRAME 0828. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Mar 1, 2018
From: GEO SEMICONDUCTOR INC.
To: ROADMAP GEO LP III, AS ADMINISTRATIVE AGENT
Reel/Frame 045482/0808 →
SECURITY INTEREST Recorded Dec 26, 2017
From: GEO SEMICONDUCTOR INC.
To: ROADMAP GEO LP III, AS ADMINISTRATIVE AGENT
Reel/Frame 044958/0828 →
SECURITY INTEREST Recorded Dec 20, 2017
From: GEO SEMICONDUCTOR INC.
To: SCOTT LAKE HOLDINGS INC.
Reel/Frame 044957/0529 →
SECURITY AGREEMENT Recorded Oct 23, 2013
From: GEO SEMICONDUCTOR INC
To: BISHOPSGATE HOLDINGS CORPORATION
Reel/Frame 031479/0486 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2013
From: MAXIM INTEGRATED PRODUCTS, INC.
To: GEO SEMICONDUCTOR INC.
Reel/Frame 029677/0261 →