Flat panel display and fabrication method thereof
View Patent ↗A flat panel display and fabrication method thereof. The present invention uses four etching processes to define a second conducting layer, a doped semiconductor layer and a semiconductor layer. The first etching process is a wet etching using a first resist layer to etch the second conducting layer. The second etching process is executed with an etchant comprising oxygen to etch the doped semiconductor layer and the semiconductor layer, and the first resist layer undergoes ashing during etching so as to become a second resist layer with a channel pattern. The third etching process is another wet etching, and the second conducting layer is etched again using the second resist layer as the etching mask. The fourth etching process is executed to dry etch the doped semiconductor layer using the second resist layer as the etching mask.
1. A method for forming a flat panel display, comprising:
providing a substrate;
forming a first conducting layer on the substrate, the first conducting layer comprising a gate electrode;
covering a first insulating layer on the first conducting layer and the substrate;
covering a semiconductor layer on the first insulating layer;
covering a doped semiconductor layer on the semiconductor layer;
covering a second conducting layer on the doped semiconductor layer;
forming a first resist layer on the second conducting layer;
performing a first wet etching on the second conducting layer such that the doped semiconductor layer is exposed and the first resist layer overhangs an edge of the second conducting layer, wherein a gap between the edge of the second conducting layer and edge of the first resist layer is a first distance;
performing a first dry etching on the doped semiconductor layer and the semiconductor layer, wherein the first resist layer undergoes partial ashing to a second resist layer;
performing a second wet etching on the second conducting layer such that the second resist layer overhangs the edge of the second conducting layer, wherein a gap between the edge of the second conducting layer and an edge of the doped semiconductor layer is a second distance, and a source electrode and a drain electrode are defined within the second conducting layer; and
performing a second dry etching on the doped semiconductor layer to form a source and a drain within the doped semiconductor layer.
2. The method for forming the flat panel display of claim 1 , wherein the first distance of the step of performing the first wet etching on the second conducting layer is about 1 μm.
3. The method for forming the flat panel display of claim 1 , wherein the second distance of the step of performing the second wet etching on the second conducting layer is smaller than about 2 μm.
4. The method for forming the flat panel display of claim 1 , wherein the doped semiconductor layer and the semiconductor layer of the step of performing the first dry etching are dry etched with the etchant comprising oxygen at a flow rate of about 100-1000 sccm.
5. The method for forming the flat panel display of claim 1 , further comprising:
covering a second insulating layer on the second conducting layer, the doped semiconductor layer, the semiconductor layer and the first insulating layer;
forming an opening within the second insulating layer to expose a portion of the drain electrode; and
forming a pixel electrode on the second insulating layer and the pixel electrode connecting with the drain electrode via the opening.
6. The method for forming the flat panel display of claim 1 , wherein the semiconductor layer of the step of covering a semiconductor layer on the first insulating layer is an amorphous layer.
7. The method for forming the flat panel display of claim 1 , wherein the doped semiconductor layer of the step of covering a doped semiconductor layer on the semiconductor layer is an n-type doped amorphous silicon layer.
8. The method for forming the flat panel display of claim 1 , wherein a size, which is of the second resist layer of the step of performing the first dry etching on the doped semiconductor layer and the semiconductor layer, is smaller than a size of the first resist layer.
9. The method for forming the flat panel display of claim 1 , wherein material of the first insulating layer of the step of covering the first insulating layer on the first conducting layer and the substrate comprises organic material, silicon oxide or silicon nitride.
10. The method for forming the flat panel display of claim 5 , wherein material of the second insulating layer of the step of covering the second insulating layer on the second conducting layer, the doped semiconductor layer, the semiconductor layer and the first insulating layer comprises organic material, silicon oxide or silicon nitride.