Clock skew compensation
A clock distribution approach includes distributing a clock signal from a clock tree to a first set of circuit elements characterized by a first circuit characteristic; and distributing a clock signal from a sub-tree of the clock tree to a second set of circuit elements characterized by a second circuit characteristic different from the first circuit characteristic.
1. An integrated circuit, comprising:
a first clock distribution network distributing a first clock signal to a first set of circuit elements, the first set of circuit elements and at least a portion of the first clock distribution network located in a portion of the circuit characterized by a first circuit characteristic; and
a second clock distribution network distributing a second clock signal to a second set of circuit elements, the second set of circuit elements and at least a portion of the second clock distribution network located in a portion of the circuit characterized by a second circuit characteristic different from the first circuit characteristic;
wherein the second clock distribution network includes a source of the second clock signal derived from a portion of the first clock distribution network located in the portion of the circuit characterized by the second circuit characteristic; and
wherein the first circuit characteristic comprises a first supply voltage source for the first set of circuit elements, and the second circuit characteristic comprises a second supply voltage source for the second set of circuit elements; and
wherein the first supply voltage source comprises a varying supply voltage source, and the second supply voltage source comprises a substantially fixed supply voltage source.
2. The integrated circuit of claim 1 , wherein the first and second circuit characteristics comprise different average clock signal delays.
3. The integrated circuit of claim 1 , wherein the first and second circuit characteristics comprise different clock signal delay variations.
4. The integrated circuit of claim 1 , wherein the substantially fixed supply voltage source comprises a regulated voltage source.
5. The integrated circuit of claim 1 , wherein the varying supply voltage source comprises at least one battery.
6. The integrated circuit of claim 1 , wherein the first clock distribution network has a tree topology.
7. The integrated circuit of claim 6 , wherein the second clock distribution network has a tree topology.
8. The integrated circuit of claim 1 , wherein the first and second sets of circuit elements each include at least one bistable multivibrator circuit element.
9. The integrated circuit of claim 8 , wherein at least one bistable multivibrator circuit element in the second set provides an input signal for a bistable multivibrator circuit element in the first set.
10. The integrated circuit of claim 9 , wherein at least one bistable multivibrator circuit element in the first set provides an input signal for a bistable multivibrator circuit element in the second set.
11. The integrated circuit of claim 9 , wherein the input signal is derived from an output of the bistable multivibrator circuit element in the second set after propagating through one or more logic gates.
12. A method for distributing clock signals to circuit elements, comprising:
distributing a clock signal from a clock tree to a first set of circuit elements characterized by a first circuit characteristic; and
distributing a clock signal from a sub-tree of the clock tree to a second set of circuit elements characterized by a second circuit characteristic different from the first circuit characteristic;
wherein the first circuit characteristic comprises a first supply voltage source for the first set of circuit elements, and the second circuit characteristic comprises a second supply voltage source for the second set of circuit elements; and
wherein the first supply voltage source comprises a varying supply voltage source, and the second supply voltage source comprises a substantially fixed supply voltage source.
13. The method of claim 12 , wherein the first and second circuit characteristics comprise different average clock signal delays.
14. The method of claim 12 , wherein the first and second circuit characteristics comprise different clock signal delay variations.
15. The method of claim 12 , wherein the substantially fixed supply voltage source comprises a regulated voltage source.
16. The method of claim 12 , wherein the varying supply voltage source comprises at least one battery.
17. An integrated circuit, comprising:
a first clock distribution network distributing a first clock signal to a first set of circuit elements, the first set of circuit elements and at least a portion of the first clock distribution network located in a portion of the circuit characterized by a first circuit characteristic; and
a second clock distribution network distributing a second clock signal to a second set of circuit elements, the second set of circuit elements and at least a portion of the second clock distribution network located in a portion of the circuit characterized by a second circuit characteristic different from the first circuit characteristic;
wherein the second clock distribution network includes a source of the second clock signal derived from a portion of the first clock distribution network located in the portion of the circuit characterized by the second circuit characteristic; and
wherein the first and second sets of circuit elements each include at least one bistable multivibrator circuit element; and
wherein at least one bistable multivibrator circuit element in the second set provides an input signal for a bistable multivibrator circuit element in the first set.
18. The integrated circuit of claim 17 , wherein the first and second circuit characteristics comprise different average clock signal delays.
19. The integrated circuit of claim 17 , wherein the first and second circuit characteristics comprise different clock signal delay variations.
20. The integrated circuit of claim 17 , wherein the first circuit characteristic comprises a first supply voltage source for the first set of circuit elements, and the second circuit characteristic comprises a second supply voltage source for the second set of circuit elements.
21. The integrated circuit of claim 20 , wherein the first supply voltage source comprises a varying supply voltage source, and the second supply voltage source comprises a substantially fixed supply voltage source.
22. The integrated circuit of claim 21 , wherein the substantially fixed supply voltage source comprises a regulated voltage source.
23. The integrated circuit of claim 21 , wherein the varying supply voltage source comprises at least one battery.
24. The integrated circuit of claim 17 , wherein the first clock distribution network has a tree topology.
25. The integrated circuit of claim 24 , wherein the second clock distribution network has a tree topology.
26. The integrated circuit of claim 17 , wherein at least one bistable multivibrator circuit element in the first set provides an input signal for a bistable multivibrator circuit element in the second set.
27. The integrated circuit of claim 17 , wherein the input signal is derived from an output of the bistable multivibrator circuit element in the second set after propagating through one or more logic gates.