Memory module with load capacitance added to clock signal input
View Patent ↗A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.
1. A memory module with a multiple-rank configuration comprising:
a phase-locked loop circuit for distributing a clock signal to memories; and
a load capacity provided at a clock signal input portion of the phase-locked loop circuit in order to match input timings of a clock signal and a data strobe signal entering each of the memories,
wherein another load capacity having a half of a capacity value of the load capacity is provided between complementary signal lines of the clock signal as a substitute for the load capacity.
2. The memory module according to claim 1 , wherein one end of the load capacity provided within the phase-locked loop circuit is connected to a dummy pin, and a clock signal input pin of the phase-locked loop circuit is connected to the dummy pin.
3. The memory module according to claim 1 , wherein a layout design for the clock signal within a memory module board, including a characteristic impedance, a wiring length, a wiring width, wiring layers, a stub resistance value and terminal ends of a wiring extending between a clock terminal and an input pin of the phase-locked loop circuit is made equal to a layout design for the data strobe signal including a characteristic impedance, a wiring length, a wiring width, wiring layers, a stub resistance value and terminal ends of a wiring extending between a data strobe terminal and an input pin of each memory; and
the load capacity is added to the clock signal input portion of the phase-locked loop circuit whereby a total capacity value of data strobe signal input pins of the memories connected to the data strobe signal is made equal to a capacity value of the clock signal input portion of the phase-locked loop circuit.
4. The memory module according to claim 1 , wherein the load capacity is set such that a time constant of a data strobe signal line in a signal wiring transmitting the data strobe signal from a memory controller to an input pin of each memory is equal to a time constant of a clock signal line in a signal wiring transmitting the clock signal from the memory controller to an input pin of the phase-locked loop circuit.
5. A memory module with a multiple-rank configuration comprising:
a phase-locked loop circuit for distributing a clock signal to memories; and
a load capacity provided at a clock signal input portion of the phase-locked loop circuit in order to match input timings of a clock signal and a data strobe signal entering each of the memories,
wherein the load capacity is set such that a time constant of a data strobe signal line represented by a product of a sum of a stub resistance and a wiring impedance in a wiring transmitting the data strobe signal multiplied by an input pin capacity of each memory receiving the data strobe signal is equal to a time constant of a clock signal line represented by a product of a sum of the load capacity and a clock signal input pin capacity of the phase-locked loop circuit multiplied by a wiring impedance of the clock signal, and
wherein another load capacity having a half of a capacity value of the load capacity is provided between complementary signal lines of the clock signal as a substitute for the load capacity.
6. A memory module with a multiple-rank configuration comprising:
a phase-locked loop circuit for distributing a clock signal to memories: and
a load capacity provided at a clock signal input portion of the phase-locked loop circuit in order to match input timings of a clock signal and a data strobe signal entering each of the memories,
wherein the load capacity is set such that a time constant of a data strobe signal line represented by a product of a sum of a stub resistance and a wiring impedance in a wiring transmitting the data strobe signal multiplied by an input pin capacity of each memory receiving the data strobe signal is equal to a time constant of a clock signal line represented by a product of a sum of the load capacity and a clock signal input pin capacity of the phase-locked loop circuit multiplied by a wiring impedance of the clock signal, and
wherein opposite ends of another load capacity having a half of a capacity value of the load capacity and provided within the phase-locked loop circuit as a substitute for the load capacity are connected to dummy pins, respectively, and complementary clock signal input pins of the phase-locked loop circuit are connected to the dummy pins, respectively.