Thin film transistor and method of fabricating the same
View Patent ↗A bottom gate thin film transistor and method of fabricating the same are disclosed, in which a channel region is crystallized by a super grain silicon (SGS) crystallization method, including: forming a gate electrode and a gate insulating layer on an insulating substrate; forming an amorphous silicon layer on the gate insulating layer followed by forming a capping layer and a metal catalyst layer; performing heat treatment to crystallize the amorphous silicon layer into a polysilicon layer; and forming an etch stopper, source and drain regions and source and drain electrodes. The thin film transistor includes: an insulating substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; a polysilicon layer formed on the gate insulating layer and crystallized by an SGS crystallization method; and source and drain regions and source and drain electrodes formed in a predetermined region of the substrate.
1. A method of fabricating a thin film transistor, comprising:
preparing a substrate;
forming a gate electrode on the substrate;
forming a gate insulating layer on the gate electrode;
forming an amorphous silicon layer and a capping layer on the gate insulating layer;
forming a metal catalyst layer on the capping layer;
performing a first heat treatment process on the substrate to diffuse or penetrate a metal catalyst into the capping layer;
patterning the capping layer to form a capping layer pattern;
performing a second heat treatment process on the substrate to crystallize the amorphous silicon layer into the polysilicon layer.
2. The method according to claim 1 , further comprising, after patterning the capping layer to form a capping layer pattern, forming source and drain regions by an ion implantation process using the capping pattern as a mask.
3. The method according to claim 2 , wherein forming of the source and drain regions includes:
forming a highly doped silicon layer on the substrate; and patterning the silicon layer.
4. The method according to claim 1 , further comprising, after performing the second heat treatment process on the substrate to crystallize the amorphous silicon layer into the polysilicon layer, forming source and drain regions by an ion implantation process using the capping layer pattern as a mask.
5. The method according to claim 1 , wherein the capping layer pattern is an etch stopper.
6. The method according to claim 1 , wherein the first heat treatment process is performed at a temperature of 200 to 800° C. and the second heat treatment process is performed at a temperature of 400 to 1300° C.
7. The method according to claim 1 , wherein the metal catalyst layer includes a metal catalyst formed at a sheet density of 10 11 to 10 15 atoms/cm 2 .
8. The method according to claim 1 , wherein the polysilicon layer includes a metal catalyst remaining at a sheet density of 10 9 to 10 13 atoms/cm 2 .
9. The method according to claim 1 , wherein forming the metal catalyst layer is performed by depositing at least one selected from a group consisting of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd and Pt.