Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs
View Patent ↗Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
1. A semiconductor integrated circuit device having a display driver, comprising:
a gate insulating film of a first MISFET formed over a semiconductor substrate;
a gate electrode of said first MISFET formed over said gate insulating film;
first semiconductor regions formed in said semiconductor substrate, wherein said first semiconductor regions serve as part of source and drain regions of said first MISFET;
an insulating film formed in said semiconductor substrate, said insulating film being arranged between said first semiconductor regions and a semiconductor region under said gate insulating film,
second semiconductor regions formed in said semiconductor substrate and surrounding first semiconductor regions and said insulating film, wherein said second semiconductor regions serve as part of source and drain regions of said first MISFET,
wherein an impurity concentration of said first semiconductor regions is higher than an impurity concentration of said second semiconductor regions,
wherein said insulating film is thicker than said gate insulating film,
wherein ends of said gate electrode are formed over said insulating film in a direction from said source region to said drain region,
wherein said insulating film is embedded in a groove of said semiconductor substrate, and
wherein ends of said gate insulating film are formed over said insulating film in said source/drain direction.
2. A semiconductor integrated circuit device according to claim 1 , wherein said insulating film is formed before said gate insulating film.
3. A semiconductor integrated circuit device according to claim 1 , wherein the depth of said groove is at least 300 nm.
4. A semiconductor integrated circuit device according to claim 1 , wherein said first MISFET is a high breakdown voltage n-channel type MISFET, and
wherein said first and second semiconductor regions are formed in a p-type impurity region in said semiconductor substrate.
5. A semiconductor integrated circuit device according to claim 1 , wherein said first MISFET is a high breakdown voltage p-channel type MISFET, and
wherein said first and second semiconductor regions are formed in an n-type impurity region in said semiconductor substrate.
6. A semiconductor integrated circuit device according to claim 1 , wherein said first MISFET comprises sidewall films at said ends of said gate electrode.
7. A semiconductor integrated circuit device according to claim 1 , further comprising a second MISFET which includes a thinner gate insulating film than that of said first MISFET.
8. A semiconductor integrated circuit device according to claim 1 , wherein said first film is formed of a silicon oxide film.
9. A semiconductor integrated circuit device according to claim 1 , wherein said second film is formed of a silicon oxide film.
10. A semiconductor integrated circuit device according to claim 1 , wherein said gate insulating film comprises a first film and a second film.
11. A semiconductor integrated circuit device according to claim 10 , wherein said second film is thicker than said first film.
12. A semiconductor integrated circuit device according to claim 10 , wherein said first film is formed by a thermal oxidation method, and
wherein said second film is formed by a CVD method.
13. A semiconductor integrated circuit device having a display driver, comprising:
a gate insulating film of a first MISFET formed over a semiconductor substrate;
a gate electrode of said first MISFET formed over said gate insulating film;
first semiconductor regions formed in said semiconductor substrate, wherein said first semiconductor regions serve as part of source and drain regions of said first MISFET;
an insulating film formed in said semiconductor substrate, said insulating film being arranged between said first semiconductor regions and a semiconductor region under said gate insulating film,
second semiconductor regions formed in said semiconductor substrate and surrounding first semiconductor regions and said insulating film, wherein said second semiconductor regions serve as part of source and drain regions of said first MISFET,
wherein an impurity concentration of said first semiconductor regions is higher than an impurity concentration of said second semiconductor regions,
wherein said insulating film is thicker than said gate insulating film,
wherein ends of said gate electrode are formed over said insulating film in a direction from said source region to said drain region,
wherein said insulating film is embedded in a groove of said semiconductor substrate,
wherein said gate insulating film comprises a first film formed over said semiconductor substrate and a second film formed over said first film, and
wherein ends of said second film are formed over said insulating film in said source/drain direction.
14. A semiconductor integrated circuit device according to claim 13 , wherein said insulating film is formed before said gate insulating film.
15. A semiconductor integrated circuit device according to claim 13 , wherein the depth of said groove is at least 300 nm.
16. A semiconductor integrated circuit device according to claim 13 , wherein said first MISFET is a high breakdown voltage n-channel type MISFET, and
wherein said first and second semiconductor regions are formed in a p-type impurity region in said semiconductor substrate.
17. A semiconductor integrated circuit device according to claim 13 , wherein said first MISFET is a high breakdown voltage p-channel type MISFET, and
wherein said first and second semiconductor regions are formed in an n-type impurity region in said semiconductor substrate.
18. A semiconductor integrated circuit device according to claim 13 , wherein said first MISFET comprises sidewall films at said ends of said gate electrode.
19. A semiconductor integrated circuit device according to claim 13 , further comprising a second MISFET which includes a thinner gate insulating film than that of said first MISFET.
20. A semiconductor integrated circuit device according to claim 13 , wherein said second film is thicker than said first film.
21. A semiconductor integrated circuit device according to claim 13 , wherein said first film is formed by a thermal oxidation method, and
wherein said second film is formed by a CVD method.
22. A semiconductor integrated circuit device according to claim 13 , wherein said first film is formed of a silicon oxide film.
23. A semiconductor integrated circuit device according to claim 13 , wherein said second film is formed of a silicon oxide film.