IP Library Granted Patent US 7,822,207
Granted Patent B2
US 7,822,207 · App. 11/615,225 · Granted Oct 26, 2010

Key protection mechanism

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Quick Facts
Patent No.
US 7,822,207
App. No.
11/615,225
Granted
Oct 26, 2010
Kind
B2
Abstract

A method of protecting secret key integrity in a hardware cryptographic system includes first obtaining an encryption result and corresponding checksum of known data using the secret key, saving those results, then masking the secret key and storing the masked key. When the masked key is to be used in a cryptographic application, the method checks key integrity against fault attacks by decrypting the prior encryption results using the masked key. If upon comparison, the decryption result equals valid data, then the key's use in the cryptographic system can proceed. Otherwise, all data relating to the masked key is wiped from the system and fault injection is flagged.

Claims (27)

1. A method of protecting secret key integrity in a hardware cryptographic system subject to fault attacks, the method comprising:

obtaining an encryption result and corresponding checksum from known data and a secret key to be protected;

masking the secret key to obtain a masked key;

loading the masked key into a key register;

at any time prior to using a masked key in the hardware cryptographic system, first checking the integrity of the masked key by decrypting the encryption result with the masked key to obtain a decryption result and comparing the decryption result to valid data; and

if the decryption result is not equal to valid data, then wiping all data relating to the masked key and flagging a fault injection.

2. The method as in claim 1 , wherein obtaining an encryption result and corresponding checksum comprises loading the secret key to be protected in plain into a key register;

presenting known data to an encryption algorithm and encrypting the known data using the secret key to obtain the encryption result;

performing a checksum computation upon the encryption result to obtain the corresponding checksum; and

saving the encryption result and checksum in a secure memory.

3. The method as in claim 2 , wherein the checksum computation is a cyclic redundancy check (CRC) routine.

4. The method as in claim 1 , wherein masking the secret key comprises generating random bytes using random number generator hardware and applying the random bytes to the secret key using a masking routine.

5. The method as in claim 4 , wherein the masking routine is a bitwise-XOR operation of the random bytes and the secret key.

6. The method as in claim 4 , wherein the random bytes are generated after seeding the random number generator hardware with a known seed, different seeds producing different sequences of random bytes.

7. A method of protecting secret key integrity in a hardware cryptographic system subject to fault attacks, the method comprising:

loading a secret key to be protected in plain into a key register;

presenting known data to an encryption algorithm and encrypting the known data using the secret key to obtain an encryption result;

performing a checksum computation upon the encryption result to obtain a corresponding checksum; and

saving the encryption result and checksum, and clearing the secret key from the key register;

generating random bytes using random number generator hardware and applying the random bytes to the secret key using a masking routine to obtain a masked key;

loading the masked key into a key register;

decrypting the saved encryption result with the masked key to obtain a decryption result;

comparing the decryption result to valid data; and

if the decryption result is not equal to valid data, then wiping all data relating to the masked key and flagging a fault injection, but if the decryption result is equal to valid data, then certifying the integrity of the masked key for use in the cryptographic system.

8. The method as in claim 7 , wherein the checksum computation is a cyclic redundancy check (CRC) routine.

9. The method as in claim 7 , wherein the masking routine is a bitwise-XOR operation of the random bytes and the secret key.

10. The method as in claim 7 , wherein the random bytes are generated after seeding the random number generator hardware with a known seed, different seeds producing different sequences of random bytes.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2019
From: VERIMATRIX
To: RAMBUS INC.
Reel/Frame 051262/0413 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Nov 21, 2019
From: GLAS SAS, AS AGENT
To: INSIDE SECURE
Reel/Frame 051076/0306 →
CHANGE OF ADDRESS Recorded Oct 16, 2019
From: VERIMATRIX
To: VERIMATRIX
Reel/Frame 050733/0003 →
CHANGE OF NAME Recorded Oct 7, 2019
From: INSIDE SECURE
To: VERIMATRIX
Reel/Frame 050647/0428 →
SECURITY INTEREST Recorded Feb 27, 2019
From: INSIDE SECURE
To: GLAS SAS, AS SECURITY AGENT
Reel/Frame 048449/0887 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2012
From: ATMEL ROUSSET S.A.S.
To: INSIDE SECURE
Reel/Frame 028644/0509 →