Host processor assisted fast re-synchronization techniques for DVB-H systems

1. A method of performing re-synchronization for a Digital Video Broadcasting over Handheld (DVB-H) receiver, said method comprising:

performing a time division multiplexing (TDM) data burst transmission sequence on bits of data received by said DVB-H receiver;

performing a data bit re-synchronization sequence on said DVB-H receiver, wherein said data bit re-synchronization sequence comprises synchronization of said DVB-H receiver after wake up for receiving a next sequence of a data burst;

removing an on-chip timer and internal state registers in said DVB-H receiver; and

allowing said DVB-H receiver to power off in between receipt of data bursts.

2. The method of claim 1 , wherein said data bit re-synchronization sequence comprises:

performing an automatic gain control (AGC) lock process comprising measuring and comparing A/D output signal strength with a pre-set threshold;

performing a mode and guard detecting process comprising detecting transmission mode and guard information;

performing a frequency offset estimation process comprising obtaining fine-frequency offset information;

performing a transit parameter signaling (TPS) detection process comprising decoding TPS information to program blocks of said DVB-H receiver;

performing a timing and carrier loop lock process comprising adjusting timing and frequency offsets based on a digital phased lock loop; and

performing an equalizer delay process comprising estimating and equalizing channel state information.

3. The method of claim 1 , further comprising using a processor communicatively linked with said DVB-H receiver from a host data transmission device to use a counter to count down a period of time after which the host processor turns on a demodulator in said DVB-H receiver.

4. The method of claim 3 , further comprising said host processor:

(a) reading a value of said period of time from said DVB-H receiver;

(b) turning off said demodulator;

(c) initiating a timer counting said period of time; and

(d) turning on said demodulator after said period of time being counted on said timer expires.

5. The method of claim 4 , further comprising repeating steps (a) through (d) for every burst of data.

6. The method of claim 2 , further comprising storing, in said host processor, a last value of an AGC control word when said DVB-H receiver enters into a sleep mode of operation, wherein said last value of said AGC control word is used to initialize a new AGC control word when said DVB-H receiver turns on from said sleep mode of operation.

7. The method of claim 2 , further comprising:

storing, in said host processor, a detected mode and guard from an immediately preceding data burst when said DVB-H receiver enters into a sleep mode of operation; and

utilizing the stored detected mode and guard when said DVB-H receiver turns on from said sleep mode of operation.

8. The method of claim 1 , further comprising:

storing, in said host processor, an estimated coarse frequency offset from an immediately preceding data burst when said DVB-H receiver enters into a sleep node of operation; and

utilizing the stored estimated coarse frequency offset to initialize a coarse frequency offset for an incoming data burst when said DVB-H receiver turns on from said sleep mode of operation.

9. The method of claim 1 , further comprising:

storing, in said host processor, internal states of timing and carrier frequency tracking loops from an immediately preceding data burst when said DVB-H receiver enters into a sleep node of operation; and

utilizing the stored internal states of timing and carrier frequency tracking loops to initialize a coarse frequency offset for an incoming data burst when said DVB-H receiver turns on from said sleep mode of operation.

10. The method of claim 1 , further comprising using said host processor to correct an orthogonal frequency-division multiplexing (OFDM) symbol number, correct a frame number, and correct a Fast Fourier Transform (FFT) trigger point when said DVB-H receiver turns on from a sleep mode of operation.

11. The method of claim 1 , wherein the removing process reduces the time to perform said re-synchronization in said DVB-H receiver.

12. A method of performing re-synchronization for a Digital Video Broadcasting over Handheld (DVB-H) receiver, said method comprising:

performing a time division multiplexing (TDM) data burst transmission sequence on bits of data received by said DVB-H receiver;

performing a data bit re-synchronization sequence on said DVB-H receiver, wherein said data bit re-synchronization sequence comprises synchronization of said DVB-H receiver after wake up for receiving a next sequence of a data burst;

removing an on-chip timer and internal state registers in said DVB-H receiver; and

powering said DVB-H receiver off in between receipt of data bursts,

wherein said method further comprises using a processor from a host data transmission device to use a counter to count down a period of time after which the host processor turns on a demodulator in said DVB-H receiver,

wherein said method further comprises said host processor:

(a) reading a value of said period of time from said DVB-H receiver;

(b) turning off said demodulator;

(c) initiating a timer counting said period of time; and

(d) turning on said demodulator after said period of time being counted on said timer expires,

wherein the removing reduces the time to perform said re-synchronization in said DVB-H receiver.

13. The method of claim 12 , wherein said data bit re-synchronization sequence comprises:

performing an automatic gain control (AGC) lock process comprising measuring and comparing A/D output signal strength with a pre-set threshold;

performing a mode and guard detecting process comprising detecting transmission mode and guard information;

performing a frequency offset estimation process comprising obtaining fine-frequency offset information;

performing a transit parameter signaling (TPS) detection process comprising decoding TPS information to program blocks of said DVB-H receiver;

performing a timing and carrier loop lock process comprising adjusting timing and frequency offsets based on a digital phased lock loop; and

performing an equalizer delay process comprising estimating and equalizing channel state information.

14. The method of claim 12 , wherein said method further comprises repeating steps (a) through (d) for every burst of data.

15. The method of claim 13 , wherein said method further comprises storing, in said host processor, a last value of an AGC control word when said DVB-H receiver enters into a sleep mode of operation, wherein said last value of said AGC control word is used to initialize a new AGC control word when said DVB-H receiver turns on from said sleep mode of operation.

16. The method of claim 13 , wherein said method further comprises:

storing, in said host processor, a detected mode and guard from an immediately preceding data burst when said DVB-H receiver enters into a sleep mode of operation; and

utilizing the stored detected mode and guard when said DVB-H receiver turns on from said sleep mode of operation.

17. The method of claim 12 , wherein said method further comprises:

storing, in said host processor, an estimated coarse frequency offset from an immediately preceding data burst when said DVB-H receiver enters into a sleep node of operation; and

utilizing the stored estimated coarse frequency offset to initialize a coarse frequency offset for an incoming data burst when said DVB-H receiver turns on from said sleep mode of operation.

18. The method of claim 12 , wherein said method further comprises:

storing, in said host processor, an internal states of timing and carrier frequency tracking loops from an immediately preceding data burst when said DVB-H receiver enters into a sleep mode of operation; and

utilizing the stored internal states of timing and carrier frequency tracking loops to initialize a coarse frequency offset for an incoming data burst when said DVB-H receiver turns on from said sleep mode of operation.

19. The method of claim 12 , wherein said method further comprises using said host processor to correct an orthogonal frequency-division multiplexing (OFDM) symbol number, correct a frame number, and correct a Fast Fourier Transform (FFT) trigger point when said DVB-H receiver turns on from a sleep mode of operation.

20. A system of performing re-synchronization for a Digital Video Broadcasting over Handheld (DVB-H) receiver, comprising an on-chip timer and internal state registers, said system comprising:

a first logic unit that performs a time division multiplexing (TDM) data burst transmission sequence on bits of data received by said DVB-H receiver;

a second logic unit that performs a data bit re-synchronization sequence on said DVB-H receiver, wherein said data bit re-synchronization sequence comprises synchronization of said DVB-H receiver after wake up for receiving a next sequence of a data burst, and wherein said data bit re-synchronization sequence comprises:

performing an automatic gain control (AGC) lock process comprising measuring and comparing A/D output signal strength with a pre-set threshold;

performing a mode and guard detecting process comprising detecting transmission mode and guard information;

performing a frequency offset estimation process comprising obtaining fine- frequency offset information;

performing a transit parameter signaling (TPS) detection process comprising decoding TPS information to program blocks of said DVB-H receiver;

performing a timing and carrier loop lock process comprising adjusting timing and frequency offsets based on a digital phased lock loop; and

performing an equalizer delay process comprising estimating and equalizing channel state information;

a host processor communicatively linked with said DVB-H receiver from a host data transmission device to use a counter to count down a period of time after which said host processor turns on a demodulator in said DVB-H receiver;

means for removing said on-chip timer and internal state registers in said DVB-H receiver; and

a cycle clock that powers said DVB-H receiver off in between receipt of data bursts,

wherein the removing means reduces the time to perform said re-synchronization in said DVB-H receiver,

wherein said host processor:

reads a value of said period of time from said DVB-H receiver;

turns off said demodulator;

initiates a timer counting said period of time;

turns on said demodulator after said period of time being counted on said timer expires;

stores a last value of an AGC control word when said DVB-H receiver enters into a sleep mode of operation, wherein said last value of said AGC control word is used to initialize a new AGC control word when said DVB-H receiver turns on from said sleep mode of operation;

stores a detected mode and guard from an immediately preceding data burst when said DVB-H receiver enters into a sleep mode of operation, wherein the stored detected mode and guard is used when said DVB-H receiver turns on from said sleep mode of operation;

stores an estimated coarse frequency offset from an immediately preceding data burst when said DVB-H receiver enters into a sleep node of operation, wherein the stored estimated coarse frequency offset initializes a coarse frequency offset for an incoming data burst when said DVB-H receiver turns on from said sleep mode of operation;

stores internal states of timing and carrier frequency tracking loops from an immediately preceding data burst when said DVB-H receiver enters into a sleep node of operation, wherein the stored internal states of timing and carrier frequency tracking loops initialize a coarse frequency offset for an incoming data burst when said DVB-H receiver turns on from said sleep mode of operation; and

corrects an orthogonal frequency-division multiplexing (OFDM) symbol number, correct a frame number, and correct a Fast Fourier Transform (FFT) trigger point when said DVB-H receiver turns on from a sleep mode of operation.