IP Library Granted Patent US 7,915,117
Granted Patent B2
US 7,915,117 · App. 11/616,943 · Granted Mar 29, 2011

Method for forming a pixel of an electroluminescence device having storage capacitors

Assignee: Au Optronics Corporation
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Quick Facts
Patent No.
US 7,915,117
App. No.
11/616,943
Granted
Mar 29, 2011
Kind
B2
Abstract

An electroluminescence (EL) device includes a substrate and a plurality of pixels formed on the substrate. Each pixel includes a first area including at least a first capacitor and a second capacitor, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and a second conductive layer over the first dielectric layer, and the second capacitor including the second conductive layer, a second dielectric layer over the second conductive layer, and a third conductive layer over the second dielectric layer, and a second area including a first semiconductor layer formed on the substrate, a first gate oxide layer over the first semiconductor layer, and a fourth conductive layer over the first gate oxide layer.

Claims (23)

1. A method for forming a pixel of an electroluminescence device, comprising:

providing a substrate;

defining at least a first area for capacitors and a second area for a transistor on the substrate;

forming a gate oxide layer over the first area;

forming a first conductive layer over the gate oxide layer over the first area;

forming a first dielectric layer over the first conductive layer over the first area;

forming a second conductive layer over the first dielectric layer over the first area;

forming a second dielectric layer over the second conductive layer over the first area;

forming a capping nitride on the second dielectric layer, wherein the capping nitride has an opening to expose a portion of the second dielectric layer over the second conductive layer;

forming an organic layer over the capping nitride to contact the second dielectric layer via the opening of the capping nitride;

forming a third conductive layer over the organic layer over the first area,

forming a semiconductor layer over the second area without over the first area;

forming a gate oxide layer contacting with the substrate over the first area;

forming a fourth conductive layer over the gate oxide layer over the second area;

wherein the first conductive layer over the first area is connectable to a power supply voltage, and wherein the first conductive layer, the first dielectric layer, and the second conductive layer over the first area collectively form a first one of the capacitors over the first area, the second conductive layer, the second dielectric layer directly over the second conductive layer, the organic layer directly over the second dielectric layer, and the third conductive layer, which is directly over the organic layer, over the first area collectively form a second one of the capacitors over the first area, and the semiconductor layer, the gate oxide layer, and the fourth conductive layer over the second area collectively form a transistor, and wherein the gate oxide layer in the first area is formed directly on the substrate; and

forming a seventh conductive layer contacting the semiconductor layer, wherein the seventh conductive layer is formed of the same conductive film as the second conductive layer.

2. The method of claim 1 , wherein forming the first conductive layer and forming the fourth conductive layer comprise forming the first conductive layer and the fourth conductive layer using the same material, wherein forming the first dielectric layer comprises forming a layer of interlayer dielectric (ILD), and wherein forming the second dielectric layer comprises forming a layer of passivation silicon nitride.

3. The method of claim 2 , further comprising forming the second conductive layer over the second area to provide contact to the semiconductor layer over the second area.

4. The method of claim 2 , further comprising:

defining a third area for an organic light-emitting diode (OLED) on the substrate;

forming a fifth conductive layer over the third area, wherein the organic layer is over the fifth conductive layer over the third area; and

forming the third conductive layer over the organic layer over the third area, wherein the fifth conductive layer, the organic layer, and the third conductive layer over the third area collectively form the OLED.

5. The method of claim 1 , wherein the second dielectric layer has a via hole outside the first area, the method further comprising forming an ITO pattern between the second dielectric layer and the capping nitride, wherein the ITO pattern is electrically connected with the seventh conductive layer through the via hole of the second dielectric layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2023
From: AUO CORPORATION
To: OPTRONIC SCIENCES LLC
Reel/Frame 064658/0572 →
CHANGE OF NAME Recorded May 25, 2023
From: AU OPTRONICS CORPORATION
To: AUO CORPORATION
Reel/Frame 063785/0830 →
Continuity (2)
Division 11005648 · Dec 7, 2004
Related Publication 20070111407A1 · May 17, 2007