Method and apparatus for reducing intra-device interference

1. A method of counteracting electro-magnetic interference (EMI) in an electronic device, comprising:

generating a first modulated clock signal as the product of a high frequency clock signal and a low frequency clock signal, the low frequency clock signal having a duty cycle, and wherein the first modulated clock signal is radiated to at least one radio frequency component of the device;

generating a second modulated clock signal as the product of the high frequency clock signal and the low frequency clock signal where the low frequency clock signal is applied with an inverted duty cycle; and

coupling the second modulated clock signal to the at least one radio frequency component whereby the second modulated clock signal counteracts harmonic content of the first modulated clock signal at the at least one radio frequency component.

2. A method of counteracting EMI as defined in claim 1 , wherein the first clock signal has a frequency greater than 1 megahertz.

3. A method of counteracting EMI as defined in claim 1 , wherein generating the first and second modulated clock signals comprises switching the high frequency clock signal with the low frequency clock signal.

4. A method of counteracting EMI as defined in claim 1 , wherein coupling the second modulated clock signal comprises coupling the second modulated clock signal to a receiver amplifier of the electronic device.

5. A method of counteracting EMI as defined in claim 4 , wherein coupling the second modulated clock signal to the receiver amplifier comprises coupling the second modulated clock signal into an input of the receiver amplifier through an impedance.

6. A method of counteracting EMI as defined in claim 5 , further comprising setting a value of the impedance so that the magnitude of the second modulated clock signal at the receiver amplifier is substantially equal to the magnitude of the first modulated clock signal at the receiver amplifier.

7. An electronic device, comprising:

a high frequency clock source generating a high frequency clock signal;

a low frequency clock source generating a low frequency clock signal;

a first switch means coupled to the high frequency clock source and the low frequency clock source for switching the high frequency clock signal with the low frequency clock signal to generate a first modulated clock signal at an output of the first switch means;

a second switch means coupled to the high frequency clock source and the low frequency clock source for switching the high frequency clock signal with an inverse of the low frequency clock signal to generate a second modulated clock signal at an output of the second switch means;

a digital circuit coupled to the output of the first switch means being clocked by the first modulated clock signal; and

a radio frequency receiver having a receiver amplifier;

wherein the first modulated clock signal is coupled into the receiver amplifier by radiation from a conductor between the output of the first switch means and the digital circuit; and

wherein the second modulated clock signal is coupled into the receiver amplifier to counteract harmonic content of the first modulated clock signal at the receiver amplifier.

8. An electronic device as defined in claim 7 , wherein the digital circuit includes a synchronous dynamic random access memory.

9. An electronic device as defined in claim 7 , wherein the second modulated clock signal is coupled into the receiver amplifier via a radiator conductor.

10. An electronic device as defined in claim 7 , wherein the second modulated clock signal is conductively coupled into the receiver amplifier via an attenuator.

11. An electronic device as defined in claim 10 , wherein the attenuator attenuates a magnitude of the second modulated clock signal at the receiver amplifier such that it is substantially equal to the magnitude of the first modulated clock signal at the receiver amplifier.

12. An electronic device as defined in claim 7 , wherein the high frequency clock source has a frequency of at least one megahertz.

13. A method for reducing radio frequency interference in an electronic device, comprising:

generating a first amplitude modulated (AM) signal within the device, the AM signal having harmonic content in a receive band in which the electronic device receives radio frequency signals, the harmonic content coupling into a receiver of the electronic device;

generating a second AM signal from the first AM signal by inverting the modulation of the first AM signal; and

coupling the second AM signal to the receiver of the electronic device to reduce the harmonic content of the first AM signal at the receiver.

14. A method for reducing radio frequency interference as defined in claim 13 , wherein generating the first AM signal comprises generating a modulated clock signal by the product of a high frequency clock signal and a low frequency clock signal.

15. A method for reducing radio frequency interference as defined in claim 14 , wherein the modulated clock signal is provided to a digital circuit of the electronic device.

16. A method for reducing radio frequency interference as defined in claim 13 , wherein coupling the second AM signal to the receiver is performed by radiating the second AM signal.

17. A method for reducing radio frequency interference as defined in claim 13 , wherein coupling the second AM signal to the receiver is performed by conductively coupling the second AM signal to an input of the receiver through an attenuator.

18. A method for reducing radio frequency interference as defined in claim 17 , further comprising adjusting the attenuator so that the magnitude of the second AM signal is substantially equal to the magnitude of the first AM signal at the input of the receiver.