Capacitance multiplier circuit
View Patent ↗An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise.
1. An integrated circuit including a capacitance multiplier, comprising:
a reference capacitor coupled between a first node and a second node, wherein the reference capacitor has a reference capacitor current; and
a current mirror arrangement coupled between the second node and a point of reference potential, wherein the current mirror arrangement includes
a first transistor Q 1 having a first terminal coupled to the second node,
a second transistor Q 2 having a first terminal coupled to the first node and
an operation amplifier coupled between the second node and a second terminal of the first transistor and the second transistor Q 2 and the point of reference potential,
wherein the current mirror arrangement has a current gain factor N, and wherein the current mirror arrangement varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current.
2. The integrated circuit as recited in claim 1 , wherein the current mirror arrangement includes:
a first resistor R 1 coupled between the second terminal of the first transistor Q 1 and an output of the operation amplifier, and
a second resistor R 2 coupled between the second terminal of the second transistor Q 2 and the output of the and the operation amplifier.
3. The integrated circuit as recited in claim 2 , wherein the first resistor R 1 and the second resistor R 2 are configured in such a way that reduces the amount of noise introduced to the capacitance multiplier by the first transistor Q 1 and the second transistor Q 2 .
4. The integrated circuit as recited in claim 1 , wherein the current gain factor N is the ratio of the area of Q 2 to the area of Q 1 .
5. The integrated circuit as recited in claim 1 , further comprising a bias current source arrangement coupled to the reference capacitor and coupled to the current mirror arrangement.
6. The integrated circuit as recited in claim 1 , wherein the current mirror arrangement is configured in such a way that reduces the amount of parasitic resistance within the capacitance multiplier.
7. An integrated circuit including a phase-locked loop (PLL) loop filter circuit, comprising:
a loop filter capacitor coupled between a first node and a first intermediate node;
a loop filter resistor coupled between the first node and the first intermediate node;
a capacitance multiplier coupled between the intermediate node and a point of reference potential,
wherein the capacitance multiplier includes
a reference capacitor coupled between the first intermediate node and a second intermediate node, wherein the reference capacitor has a reference capacitor current associated therewith, and
a current mirror arrangement coupled between the second intermediate node and the point of reference potential, wherein the current mirror arrangement includes
a first transistor Q 1 having a first terminal coupled to the second intermediate node,
a second transistor Q 2 having a first terminal coupled to the first intermediate node, and
an operation amplifier coupled between the second intermediate node and a second terminal of the first transistor and, the second transistor Q 2 and the point of reference potential,
wherein the current mirror arrangement is configured in such a way that reduces the amount of parasitics within the capacitance multiplier.
8. The integrated circuit as recited in claim 7 , wherein the current mirror arrangement is configured in such a way that reduces the amount of noise introduced to the capacitance multiplier by at least a portion of the current mirror arrangement.
9. The integrated circuit as recited in claim 7 , wherein the current mirror arrangement has a gain factor N, and wherein the current mirror arrangement varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current.
10. The integrated circuit as recited in claim 7 , wherein the current mirror arrangement includes:
a first resistor R 1 coupled between the second terminal of the first transistor Q 1 and an output of the operation amplifier, and
a second resistor R 2 coupled between the second terminal of the second transistor Q 2 and an output of the and the operation amplifier.
11. The integrated circuit as recited in claim 10 , wherein the current gain factor N is the ratio of the area of Q 2 to the area of Q 1 .
12. The integrated circuit as recited in claim 7 , further comprising a bias current source arrangement coupled to the reference capacitor and coupled to the current mirror arrangement, wherein the bias current source arrangement determines the current through the current mirror arrangement, which varies the reference capacitor current.
13. The integrated circuit as recited in claim 7 , wherein the first node is an input node, and wherein the integrated circuit further comprises a third loop filter resistor coupled between the input node and an output node, and a third loop filter capacitor coupled between the output node and the point of reference potential.