Burn-in test circuit, burn-in test method, burn-in test apparatus, and a burn-in test pattern generation program product
View Patent ↗A burn-in test circuit according to the present invention includes a scan chain formed by a plurality of scan flip-flips connected in series, a circuit under test input with an output from one of the plurality of scan flip-flops as an activation signal, and a scan chain loop circuit being configured to an output signal of the scan chain determined according to an output of the circuit under test back to the scan chain.
1. A burn-in test circuit comprising:
a scan chain formed by a plurality of scan flip-flips connected in series;
a circuit under test input with an output from one of the plurality of scan flip-flops as an activation signal; and
a scan chain loop circuit being configured to feed an output signal of the scan chain back to the scan chain, the output signal of the scan chain being determined according to an output of the circuit under test.
2. The burn-in test circuit according to claim 1 , wherein t the feedback input or an external input is selectively input to the scan chain.
3. The burn-in test circuit according to claim 1 , further comprising a circuit under test loop circuit being configured to back an output signal of the circuit under test to an input of the circuit under test,
wherein the circuit under test includes a plurality of internal combinational circuits, and
the plurality of internal combinational circuits are able to input output signals of different scan flip-flips included in the plurality of internal combinational circuits as activation signals.
4. The burn-in test circuit according to claim 3 , wherein the scan chain loop circuit and the circuit under test loop circuit are formed outside an integrated circuit where the scan chain and the circuit under test are formed thereto.
5. The burn-in test circuit according to claim 1 , wherein the scan chain loop circuit is formed outside an integrated circuit where the scan chain and the circuit under test are formed thereto.
6. A method for burn-in test for an integrated circuit having a scan chain including a plurality of scan flip-flops connected in series, and a circuit under test that lies between the plurality of scan flip-flops, the method comprising:
feeding an output signal from the scan chain determined according to an output from the circuit under test back to the scan chain;
taking the fed back signal in the plurality of scan flip-flops by a scan shift operation; and inputting the output signal from one of the plurality of scan flip-flops to the circuit under test as an activation signal.
7. The method according to claim 6 , wherein the feedback input or an external input is selectively input to the scan chain.
8. A burn-in test apparatus for executing the method according to claim 7 .
9. A burn-in test pattern generation program product for storing instructions for a burn-in test apparatus to execute the method according to claim 7 .
10. The method according to claim 6 , further comprising feeding back an output signal of the circuit under test to the circuit under test,
wherein the circuit under test includes a plurality of internal combinational circuits, and
the plurality of internal combinational circuits are able to input output signals of different scan flip-flips included in the plurality of internal combinational circuits as activation signals.
11. A burn-in test apparatus for executing the method according to claim 10 .
12. A burn-in test pattern generation program product for storing instructions for a burn-in test apparatus to execute the method according to claim 10 .
13. A burn-in test apparatus for executing the method according to claim 6 .
14. A burn-in test pattern generation program product for storing instructions for a burn-in test apparatus to execute the method according to claim 6 .