Low voltage drop and high thermal performance ball grid array package
View Patent ↗An apparatus and method for a low voltage drop and thermally enhanced integrated circuit (IC) package are described. A substantially planar substrate having a plurality of contact pads on a first surface is electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate. An IC die having a first surface is mounted to the first surface of the substrate. The IC die has a plurality of I/O pads electrically connected to the plurality of contact pads on the first surface of the substrate. A heat sink assembly is coupled to a second surface of the IC die and to a first contact pad on the first surface of the substrate to provide a thermal path from the IC die to the first surface of the substrate. The heat sink assembly can also provide an electrical path from the IC die to the first surface of the substrate. The heat sink assembly may have one or two heat sink elements to provide thermal and/or electrical connectivity between the IC die and the substrate.
1. A method for assembling an integrated circuit (IC) package, comprising the steps of:
(A) attaching a first surface of an IC die to a first surface of a substrate;
(B) coupling a heat sink assembly to a second surface of the IC die and to a first contact pad on the first surface of the substrate to provide a conductive path from the IC die to the first surface of the substrate, comprising the steps of:
(1) attaching a first surface of a first heat sink element to the second surface of the IC die; and
(2) attaching a second heat sink element to a second surface of the first heat sink element and to the first contact pad;
(C) coupling a pad located on the second surface of the IC die to a bond pad of the first heat sink element.
2. The method of claim 1 , wherein the pad is an I/O pad, wherein step (B) comprises the step of:
(3) forming an electrically conductive path from the pad of said IC die to the first contact pad.
3. The method of claim 1 , wherein step (B) comprises the step of:
attaching the heat sink assembly to the second surface of said IC die with a thermally conductive adhesive layer.
4. The method of claim 1 , wherein step (2) includes the step of:
attaching a surface of the second heat sink element to the second surface of the first heat sink element with a thermally and electrically conductive adhesive layer.
5. The method of claim 1 , wherein step (2) includes the step of:
attaching a first arm portion of the second heat sink element to the first contact pad on the first surface of the substrate.
6. The method of claim 5 , further comprising the step of:
(D) attaching a second arm portion of the second heat sink element to a second contact pad on the first surface of the substrate.
7. The method of claim 6 , further comprising the step of:
(E) electrically isolating the first arm portion and second arm portion.
8. The method of claim 1 , wherein step (2) includes the step of:
filling at least one perforation in the second heat sink element with a thermally conductive adhesive material.
9. The method of claim 1 , further comprising the step of:
(D) encapsulating the IC die and at least a portion of the heat sink assembly on the first surface of the substrate.
10. The method of claim 1 , wherein step (A) comprises the step of:
mounting the IC die in a flip chip orientation.
11. The method of claim 1 , wherein step (A) comprises the step of:
electrically coupling a conductive bump on a surface of the heat sink assembly to the pad of the IC die through a passivation opening in the second surface of the IC die, wherein the pad is an I/O pad.
12. The method of claim 1 , wherein the second surface of the first heat sink element includes the bond pad.