Descriptor prefetch mechanism for high latency and out of order DMA device
View Patent ↗A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support a linked list of descriptors, the DMA engine prefetches descriptors based on the assumption that they are sequential in memory and discards any descriptors that are found to violate this assumption. The DMA engine seeks to keep the descriptor prefetch buffer full by requesting multiple descriptors per transaction whenever possible. The bus engine fetches these descriptors from system memory and writes them to the prefetch buffer. The DMA engine may also use an aggressive prefetch where the bus engine requests the maximum number of descriptors that the buffer will support whenever there is any space in the descriptor prefetch buffer. The DMA device discards any remaining descriptors that cannot be stored.
1. A method for performing a direct memory access block move with descriptor prefetch in a direct memory access device, the method comprising:
responsive to space being available in a descriptor prefetch buffer within the direct memory access device, fetching, using one read/write transaction, a block of sequential physical memory into the descriptor prefetch buffer to speculatively prefetch a plurality of direct memory access descriptors, stored in a linked list architecture;
checking validity of the speculatively prefetched plurality of direct memory access descriptors in the descriptor prefetch buffer;
responsive to a given direct memory access descriptor being non-sequential with respect to a previous direct memory access descriptor within the speculatively prefetched plurality of direct memory access descriptors or being an invalid direct memory access descriptor, marking the given direct memory access descriptor invalid; and
processing descriptors from the descriptor prefetch buffer to perform direct memory access block moves according to the descriptors.
2. The method of claim 1 , further comprising: marking each descriptor after the given direct memory access descriptor invalid.
3. The method of claim 1 , further comprising:
responsive to the given direct memory access descriptor being sequential with respect to a previous direct memory access descriptor within the plurality of direct memory access descriptors and being a valid direct memory access descriptor, marking the given direct memory access descriptor valid.
4. A method for performing a direct memory access block move with descriptor prefetch in a direct memory access device, the method comprising:
responsive to space being available in a descriptor prefetch buffer within the direct memory access device, fetching, using one read/write transaction, a block of sequential physical memory into the descriptor prefetch buffer to speculatively prefetch a plurality of direct memory access descriptors, stored in a linked list architecture; and
processing descriptors from the descriptor prefetch buffer to perform direct memory access block moves according to the descriptors,
wherein speculatively prefetching a plurality of direct memory access descriptors comprises:
determining a number of available slots in the descriptor prefetch buffer; and
fetching the block of sequential physical memory, using one read/write transaction, having a number of speculatively prefetched direct memory access descriptors corresponding to the number of available slots;
checking validity of the plurality of speculatively prefetched direct memory access descriptors in the descriptor prefetch buffer; and
responsive to a given direct memory access descriptor being non-sequential with respect to a previous direct memory access descriptor within the plurality of speculatively prefetched direct memory access descriptors or being an invalid direct memory access descriptor, marking the given direct memory access descriptor invalid.
5. A method for performing a direct memory access block move with descriptor prefetch in a direct memory access device, the method comprising:
responsive to space being available in a descriptor prefetch buffer within the direct memory access device, fetching, using one read/write transaction, a block of sequential physical memory into the descriptor prefetch buffer to speculatively prefetch a plurality of direct memory access descriptors, stored in a linked list architecture; and
processing descriptors from the descriptor prefetch buffer to perform direct memory access block moves according to the descriptors,
wherein speculatively prefetching a plurality of direct memory access descriptors comprises:
fetching the block of sequential physical memory, using one read/write transaction, having a number of speculatively prefetched direct memory access descriptors corresponding to a maximum number of slots in the descriptor prefetch buffer;
attempting to store the number of speculatively prefetched direct memory access descriptors in the descriptor prefetch buffer; and
responsive to the descriptor prefetch buffer being full, discarding remaining direct memory access descriptors from the number of speculatively prefetched direct memory access descriptors that could not be stored in the descriptor prefetch buffer.
6. The method of claim 5 , further comprising:
responsive to space being available in the descriptor prefetch buffer, storing a given direct memory access descriptor within the number of direct memory access descriptors in the descriptor prefetch buffer.
7. The method of claim 6 , further comprising:
checking validity of the given direct memory access descriptor; and
responsive to the given direct memory access descriptor being non-sequential with respect to a previous direct memory access descriptor within the number of direct memory access descriptors or being an invalid direct memory access descriptor, marking the given direct memory access descriptor invalid.
8. The method of claim 7 , further comprising:
discarding each descriptor after the given direct memory access descriptor invalid.
9. The method of claim 6 , further comprising:
checking validity of the given direct memory access descriptor; and
responsive to the given direct memory access descriptor being sequential with respect to a previous direct memory access descriptor within the number of direct memory access descriptors and being a valid direct memory access descriptor, marking the given direct memory access descriptor valid.
10. The method of claim 4 , further comprising:
marking each descriptor after the given direct memory access descriptor invalid.
11. The method of claim 4 , further comprising:
responsive to the given direct memory access descriptor being sequential with respect to a previous direct memory access descriptor within the plurality of direct memory access descriptors and being a valid direct memory access descriptor, marking the given direct memory access descriptor valid.