IP Library Granted Patent US 7,493,464
Granted Patent B2
US 7,493,464 · App. 11/622,078 · Granted Feb 17, 2009

Sparse matrix

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Quick Facts
Patent No.
US 7,493,464
App. No.
11/622,078
Granted
Feb 17, 2009
Kind
B2
Abstract

A sparse matrix paging system is provided that dynamically allocates memory resources on demand. In some cases, this is accomplished by dynamically allocating memory resources, preferably only after a page has been requested. Such a sparse matrix paging system may allow a platform with a large linear address space to more efficiently execute on a platform with a smaller linear address space. Preferably, the sparse matrix paging system only indexes those pages that are actually requested and used in the address space on main store pages or backing store pages. Further, the backing store is preferably not involved unless the total address space allocated by the operating system exceeds the available main store pages.

Claims (36)

1. A method for accessing data in a system having a memory, the method comprising:

initializing the memory, and after the memory are initialized:

requesting data in the memory by providing a first address from a first address range;

converting the first address to a second address of a second address range, wherein the second address range is smaller than the first address range, and wherein the second address corresponds to a desired storage page; and

if the desired storage page does not yet exist in the memory, dynamically creating the desired storage page after the desired storage page is requested by the requesting step.

2. A method according to claim 1 wherein the memory includes a main memory having a storage capacity and a backing store, the method further comprising:

only storing the desired storage page on the backing store if the storage capacity of the main memory has been reached.

3. A method according to claim 1 wherein the converting step uses one or more levels of index tables, and wherein at least one of the levels of index tables is hashed using, at least in part, the first address provided by the requesting step.

4. A method according to claim 1 wherein the first address is an absolute address.

5. A method according to claim 1 wherein the second address is a virtual address.

6. A method according to claim 1 wherein the second address is a real address.

7. A data processing system, comprising:

a memory for storing one or more storage pages;

one or more requestors for making storage page requests to/from the memory by providing a corresponding first address from a first address range; and

a sparse matrix paging system for converting the first address provided by the one or more requestors to a second address of a second address range, wherein the second address range is smaller than the first address range, and for referencing a desired one of the storage pages that corresponds to the first address, the sparse matrix paging system further determining if the desired storage page does not yet exist in the memory, and if the desired storage page does not yet exist in the memory, dynamically create the desired storage page in the memory but only after the desired storage page is requested by the one or more requestors.

8. A data processing system according to claim 7 wherein the memory includes a main memory having a storage capacity and a backing store, the sparse matrix paging system only storing the desired storage page on the backing store if the storage capacity of the main memory has been reached.

9. A data processing system according to claim 7 wherein the memory includes a main memory having a storage capacity and a backing store, the sparse matrix paging system not creating or index storage pages on the backing store until the number of requested storage pages exceed an allocated capacity of the main memory.

10. A data processing system according to claim 7 wherein the sparse matrix paging system uses one or more levels of index tables when converting the first address provided by the one or more requestors to the second address of the second address range, wherein at least one of the levels of index tables is hashed using, at least in part, the first address provided by the one or more requestors.

11. A data processing system according to claim 7 wherein the first address is an absolute address.

12. A data processing system according to claim 7 wherein the second address is a virtual address.

13. A data processing system according to claim 7 wherein the second address is a real address.

14. A data processing system having a memory subsystem, comprising:

one or more requestors, each requestor providing one or more page requests; and

a paging system coupled to the one or more requestors and to the memory subsystem for determining if a requested page does not yet exist in the memory subsystem, and if the requested page does not yet exist in the memory subsystem, dynamically creating the requested page in the memory subsystem but only after the requested page is actually requested by the one or more requestors.

15. A data processing system according to claim 14 wherein the memory subsystem includes a main memory and a hard disk, and wherein the paging system dynamically creates a requested page in the main memory or hard disk only after the requested page is actually requested by the one or more requestors.

16. A data processing system according to claim 14 wherein the memory subsystem includes a main memory having a storage capacity and a backing store, the paging system dynamically creating a requested page on the backing store only after the storage capacity of the main memory has been reached.

17. A data processing system having a memory subsystem, comprising:

one or more requestors, each requestor providing one or more page requests;

a paging system coupled to the one or more requestors and to the memory subsystem for dynamically creating a requested page in the memory subsystem only after the requested page is actually requested by the one or more requestors; and

wherein the memory subsystem includes a main memory having a storage capacity and a backing store, the paging system not creating or indexing storage pages on the backing store until the number of requested pages exceed an allocated capacity of the main memory.

18. A data processing system having a memory subsystem, comprising:

one or more requestors, each requestor providing one or more page requests;

a paging system coupled to the one or more requestors and to the memory subsystem for dynamically creating a requested page in the memory subsystem only after the requested page is actually requested by the one or more requestors; and

wherein the one or more requestors provide one or more page requests to the memory subsystem by providing a corresponding first address from a first address range, and the paging system converting the first address provided by the one or more requestors to a second address of a second address range, wherein the second address range is smaller than the first address range, and wherein the first address is an absolute address.

19. A data processing system according to claim 18 wherein the second address is a virtual address.

20. A data processing system according to claim 18 wherein the second address is a real address.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 9, 2017
From: WELLS FARGO BANK, NATIONAL ASSOCIATION (SUCCESSOR TO GENERAL ELECTRIC CAPITAL CORPORATION)
To: UNISYS CORPORATION
Reel/Frame 044416/0358 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2013
From: DEUTSCHE BANK TRUST COMPANY AMERICAS, AS COLLATERAL TRUSTEE
To: UNISYS CORPORATION
Reel/Frame 030082/0545 →
RELEASE OF SECURITY INTEREST Recorded Mar 15, 2013
From: DEUTSCHE BANK TRUST COMPANY
To: UNISYS CORPORATION
Reel/Frame 030004/0619 →
SECURITY AGREEMENT Recorded Jun 27, 2011
From: UNISYS CORPORATION
To: GENERAL ELECTRIC CAPITAL CORPORATION, AS AGENT
Reel/Frame 026509/0001 →
PATENT SECURITY AGREEMENT (JUNIOR LIEN) Recorded Oct 13, 2009
From: UNISYS CORPORATION
To: DEUTSCHE BANK TRUST COMPANY AMERICAS, AS COLLATERAL TRUSTEE
Reel/Frame 023364/0098 →
PATENT SECURITY AGREEMENT (PRIORITY LIEN) Recorded Oct 12, 2009
From: UNISYS CORPORATION
To: DEUTSCHE BANK TRUST COMPANY AMERICAS, AS COLLATERAL TRUSTEE
Reel/Frame 023355/0001 →
RELEASE BY SECURED PARTY Recorded Sep 14, 2009
From: CITIBANK, N.A.
To: UNISYS CORPORATION; UNISYS HOLDING CORPORATION
Reel/Frame 023263/0631 →
RELEASE BY SECURED PARTY Recorded Jul 31, 2009
From: CITIBANK, N.A.
To: UNISYS CORPORATION; UNISYS HOLDING CORPORATION
Reel/Frame 023312/0044 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded Mar 6, 2008
From: UNISYS CORPORATION
To: CITIBANK, N.A.
Reel/Frame 020612/0305 →