IP Library Granted Patent US 8,559,996
Granted Patent B2
US 8,559,996 · App. 11/623,079 · Granted Oct 15, 2013

Power control subsystem with a plurality of current limit values

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Quick Facts
Patent No.
US 8,559,996
App. No.
11/623,079
Granted
Oct 15, 2013
Kind
B2
Abstract

A power control subsystem for controlling the supply of power transmitted to at least one node over communication cabling, the power control subsystem comprising: a plurality of references; a plurality of comparators, each of the comparators being associated with a particular one of the plurality of references; and a current limiter in communication with the plurality of comparators and arranged to limit current of the power transmitted over communication cabling responsive to the plurality of comparators.

Claims (30)

1. A power control subsystem for controlling the supply of power transmitted to at least one node over communication cabling, the power control subsystem comprising a current limiter arranged to limit current of the power transmitted over communication cabling to one of a plurality of values, the plurality of values being set by a plurality of programmable voltages, wherein said power control system further comprises:

a plurality of references, each of the references provided by a respective one of the programmable voltages, wherein each of the plurality of programmable voltages is provided by a voltage source receiving a control signal from a management circuit; and

a plurality of comparators, each of said comparators being associated with a particular one of said plurality of references,

wherein said current limiter is in communication with, and responsive to, said plurality of comparators and wherein said plurality of values are a function of said plurality of references, the current limiter providing a current limited output signal to the communication cabling.

2. The power control subsystem according to claim 1 , further comprising delay circuitry, at least one of said plurality of comparators being in communication with said current limiter via said delay circuitry.

3. The power control subsystem according to claim 1 , further comprising a switch arranged to alternatively interrupt and allow said power transmitted over communication cabling.

4. The power control subsystem according to claim 3 , wherein said current limiter and said switch are constituted of a single field effect transistor.

5. The power control subsystem according to claim 1 , wherein said plurality of references are responsive to a single management and control unit.

6. A power supply subsystem for providing electrical power to at least node over communication cabling, the power supply subsystem comprising:

a means for receiving power;

a means for outputting power for transmission to the at least one node over communication cabling; and

a circuitry arranged to limit current of the power outputted via said means for outputting power to one of a plurality of values, the plurality of values being set by a plurality of programmable voltages, wherein said circuitry arranged to limit current comprises:

a plurality of references, each of the references provided by a respective one of the programmable voltages, wherein each of the plurality of programmable voltages is provided by a voltage source receiving a control signal from a management circuit;

a plurality of comparators, each of said comparators being associated with a particular one of said plurality of references; and

a current limiter in communication with said plurality of comparators and arranged to limit, responsive to said plurality of comparators, said current of said power outputted by said means for outputting power to said one of a plurality of values, and wherein said plurality of values are a function of said plurality of references, the current limiter providing a current limited output signal to the communication cabling.

7. The power control subsystem according to claim 6 , further comprising delay circuitry, at least one of said plurality of comparators being in communication with said current limiter via said delay circuitry.

8. The power control subsystem according to claim 7 , wherein said delay circuitry comprises a timer.

9. The power control subsystem according to claim 6 , further comprising a switch arranged to alternatively interrupt and allow said power transmitted over communication cabling.

10. The power control subsystem according to claim 9 , wherein said current limiter and said switch are constituted of a single field effect transistor.

11. The power control subsystem according to claim 6 , wherein said plurality of references are responsive to a single management and control unit.

12. A method of controlling power supplied to at least one node over communication cabling, the method comprising:

outputting a power for transmission to at least one node over communication cabling; and

limiting the current of said output power to one of a plurality of values, including programming a plurality of reference voltage sources that are in communication with a current limiting circuit, each of the reference voltage sources being associated with a particular comparator of a plurality of comparators, wherein limiting the current comprises:

at each reference voltage source, receiving a respective control signal from a management circuit;

providing a plurality of references from said reference voltage sources; and

providing a current limited output signal to the communication cabling from the current limiting circuit, wherein said current limiting circuit is in communication with, and responsive to, said plurality of comparators and wherein said plurality of values are a function of the references from said plurality of reference voltage sources.

13. The method according to claim 12 , further comprising receiving an input power, said outputted power being derived from said received input power.

14. The method according to claim 12 , further comprising:

delaying an output of one of said provided plurality of references, wherein one of said plurality of values is responsive to said delayed output of said one of said provided plurality of references.

15. The method of claim 12 in which the plurality of reference voltage sources are programmed in accordance with desired operating parameters received from the at least one node.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2011
From: MICROSEMI CORP. - ANALOG MIXED SIGNAL GROUP, LTD.
To: CISCO TECHNOLOGY INC.
Reel/Frame 027430/0175 →
CHANGE OF NAME Recorded Oct 7, 2007
From: POWERDSINE, LTD.
To: MICROSEMI CORP. - ANALOG MIXED SIGNAL GROUP LTD
Reel/Frame 019920/0640 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2007
From: LEHR, AMIR; ATIAS, ILAN; KORCHARZ, DROR; PINCU, DAVID
To: POWERDSINE LTD.
Reel/Frame 018890/0192 →