IP Library Granted Patent US 7,657,680
Granted Patent B2
US 7,657,680 · App. 11/624,582 · Granted Feb 2, 2010

Multiple bus interface control using a single controller

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Quick Facts
Patent No.
US 7,657,680
App. No.
11/624,582
Granted
Feb 2, 2010
Kind
B2
Abstract

Mechanisms for configuring an integrated circuit to select one of multiple external device interfaces at a time to use during communication with external devices. The integrated circuit includes a control mechanism, a selection mechanism, and a plurality of external device interfaces. The plurality of device interfaces allow the integrated circuit to communicate with various external devices that support different communication protocols. The control mechanism is configured to designate the selection of one of the plurality of device interfaces for use in communicating with an external device. The control mechanism makes use of the selection mechanism to select the designated device interface to communicate with using the communication protocol supported by the selected interface. The communication may be receiving data from the interface or providing data to the interface. Non-selected interfaces are put in an inactive state.

Claims (37)

1. An integrated circuit comprising:

a plurality of external device interfaces for coupling the integrated circuit to a plurality of external devices, each external device interface supporting a communication protocol and each external device interface configured to couple more than one external device to the integrated circuit;

a configurable control mechanism for controlling the selection of a designated one of the plurality of external device interfaces so as to facilitate communication between the integrated circuit and an external device using the communication protocol supported by the selected device interface, wherein the configurable control mechanism receives or accesses configuration data and communication data from other components of the integrated circuit; and

a selection mechanism configured through the reception of one or more selection signals from the configurable control mechanism to select the designated one of the plurality of external device interfaces and to deactivate non-selected external device interfaces and further configured to receive communication data from the plurality of external device interfaces and to provide the received communication data to the configurable control mechanism;

wherein the selection mechanism includes:

a plurality of registers containing inactive default setting data;

a plurality of multiplexers, each multiplexer having a selection node coupled to the control mechanism, a first input node coupled to the control mechanism, a second input node coupled to one of the plurality of registers, and an output node coupled to one of the plurality of external device interfaces;

wherein each multiplexer is configured to provide data from the configurable control mechanism to the one of the plurality of external device interfaces connected to the output node of each multiplexer when the first input node of each multiplexer is selected by the selection node; and

wherein each multiplexer is configured to provide the inactive default setting data from the plurality of registers connected to second input node of each multiplexer to the one of the plurality of external device interfaces connected to the output node of each multiplexer when the second input node of each multiplexer is selected by the selection node.

2. An integrated circuit in accordance with claim 1 , wherein the configurable control mechanism is configured by microcode to designate one of the plurality of external device interfaces for selection.

3. An integrated circuit in accordance with claim 1 , wherein the configurable control mechanism includes a serial controller and a serializer and deserializer.

4. An integrated circuit in accordance with claim 3 , wherein the serial controller and the serializer and deserializer are included in one component.

5. An integrated circuit in accordance with claim 3 , wherein the serial controller and the serializer and deserializer are separate components.

6. An integrated circuit in accordance with claim 1 , wherein the selection mechanism includes:

a receive multiplexer having a selection node coupled to the control mechanism, a plurality of input nodes coupled to the plurality of external device interfaces, and an output node coupled to the control mechanism;

wherein the receive multiplexer is configured to provide data from the input node selected by the selection node to the control mechanism.

7. An integrated circuit in accordance with claim 1 , wherein the configurable control mechanism and the selection mechanism are included in one component.

8. An integrated circuit in accordance with claim 1 , wherein the configurable control mechanism and the selection mechanism are separate components.

9. An integrated circuit in accordance with claim 1 , wherein one of the plurality of external device interfaces supports a Serial Peripheral Interface (SPI) protocol.

10. An integrated circuit in accordance with claim 1 , wherein one of the plurality of external device interfaces supports an I 2 C protocol.

11. An integrated circuit in accordance with claim 1 , wherein one of the plurality of external device interfaces supports a Finisar Serial Bus (FSB) protocol.

12. An integrated circuit in accordance with claim 1 , wherein the integrated circuit is implemented in a laser transmitter/receiver.

13. An integrated circuit in accordance with claim 12 , wherein the laser transmitter/receiver is one of a 1G laser transceiver, 2G laser transceiver, 4G laser transceiver, 8G laser transceiver, or 10G laser transceiver.

14. An integrated circuit in accordance with claim 12 , wherein the laser transmitter/receiver is a laser transceiver suitable for fiber channels greater than 10G.

15. An integrated circuit in accordance with claim 12 , wherein the laser transmitter/receiver is one of a 10 Gigabit Small Form Factor Pluggable (XFP) laser transceiver, a Small Form Factor Pluggable (SFP) laser transceiver, or a Small Form Factor (SFF) laser transceiver.

16. A method that is performed in an integrated circuit comprising a control mechanism, a selection mechanism, and a plurality of external device interfaces for coupling the integrated circuit with a plurality of external devices, each external device supporting a communication protocol, the method for the control mechanism to select one of the plurality of external device interfaces for use in communicating with an external device, the method comprising:

an act of the control mechanism designating which one of the plurality of external device interfaces to select, wherein the control mechanism receives or accesses configuration data and communication data from other components of the integrated circuit and wherein the plurality of external device interfaces are configured to couple more than one external device to the integrated circuit;

an act of the control mechanism using the selection mechanism by providing a first selection signal to the selection mechanism to select the designated one of the plurality of external device interfaces;

an act of the control mechanism using the selection mechanism by providing a second selection signal to the selection mechanism to deactivate the non-selected external device interfaces; and

an act of the control mechanism sending data to and receiving data from the selected external device interface via the selection mechanism using the communication protocol supported by the selected external device interface;

wherein the selection mechanism includes a plurality of registers containing inactive default data and a plurality of multiplexers, each multiplexer having a selection node coupled to the control mechanism, a first input node coupled to the control mechanism, a second input node coupled to one of the plurality of registers, and an output node coupled to one of the plurality of external device interfaces, the method further comprising:

an act of the multiplexer coupled to the designated external device interface providing data from the control mechanism to the designated external device interface when the first input node is selected by the selection node; and

an act of the remaining multiplexers providing the inactive default data from the plurality of registers to the external device interfaces that the multiplexers are coupled to when the second input node is selected by the selection node.

17. A method in accordance with claim 16 , wherein the control mechanism includes a serial controller and a serializer and deserializer.

18. A method in accordance with claim 16 , wherein the selection mechanism includes a receive multiplexer having a selection node coupled to the control mechanism, a plurality of input nodes coupled to the plurality of external device interfaces, and an output node coupled to the control mechanism, the method further comprising;

an act of the multiplexer providing data from the input node selected by the selection node to the control mechanism.

19. A method in accordance with claim 16 , wherein the control mechanism and the selection mechanism are included in a single controller component.

Assignments (4)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
SECURITY INTEREST Recorded Jul 1, 2022
From: II-VI INCORPORATED; II-VI DELAWARE, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; PHOTOP TECHNOLOGIES, INC.; COHERENT, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 060562/0254 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: FINISAR CORPORATION
To: II-VI DELAWARE, INC.
Reel/Frame 052286/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →