Superconducting digital phase rotator
An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.
1. A phase rotator comprising:
a. a first clocked inverter receiving a clock signal and inhibiting output of a clock pulse when a decrement (DEC) pulse is received;
b. a second clocked inverter receiving the output of the first clocked inverter and inhibiting a clock pulse when an increment (INC) pulse is received;
c. a flip flop receiving the output of the second clocked inverter and producing an output signal received by a confluence buffer; and
d. a bypass line receiving an increment pulse and applying the increment pulse to a second input of the confluence buffer, bypassing the second clocked inverter and said flip flop.
2. The phase rotator of claim 1 further comprising a first clocked latch in the bypass line, whereby the clock input of the first clocked latch is obtained from the output of the first clocked inverter, and a second clocked latch receiving said clock signal and the output of the confluence buffer.
3. The phase rotator of claim 2 , wherein the output of the second clocked latch connects to one or more flip flops to divide down the phase shifted clock signal and produce a plurality of orthogonal phase shifted clock signals.
4. A multi-bit phase rotator comprising a plurality of phase rotators of claim 2 , connected such that the output of a second clocked latch of a previous phase rotator is connected to be the clock input of the first clocked inverter of a subsequent phase rotator and each phase rotator receives one bit of a decrement word and one bit of an increment word.
5. The phase rotator of claim 1 , further comprising a synchronizer circuit comprising one or more increment inputs; one or more decrement inputs; a synchronization circuit connected to one or more increment inputs and one or more decrement inputs and to a clock signal and selectively producing increment pulses and decrement pulses in response to said increment inputs and decrement inputs.
6. The phase rotator of claim 5 , wherein the synchronizer circuit comprises a binary divider chain receiving as input a master clock signal and producing a phase shifted output comprising at least orthogonal phases.
7. The phase rotator of claim 5 , wherein a first orthogonal phase and second orthogonal phase drive a multiplexer receiving decrement pulses and a multiplexer receiving increment pulses, wherein the multiplexers produce as output multiplexed increment and multiplexed decrement pulses.
8. The phase rotator of claim 5 , wherein said one or more increment inputs and said one or more decrement inputs are provided by a modulator or digital signal processor.
9. The phase rotator of claim 1 , wherein the output of the phase rotator drives an SFQ amplifier to produce a synthesized output signal.
10. A method of producing phase rotation, comprising the steps of:
a. shifting the phase of a clock in one direction by one clock period for each pulse received on an increment input; and
b. shifting the phase of a clock in another direction by one clock period for each pulse received on a decrement input;
c. wherein the pulses received on at least one of an increment input and a decrement input are SFQ pulses.
11. A method of producing phase rotation, comprising:
a. receiving a first digital multi-bit binary input;
b. receiving a second digital multi-bit binary input; and
c. producing as the output an analog phase shift in an RSFQ pulse train proportional to the difference in value between the digital multi-bit binary input and the second digital multi-bit binary input.