Reduced state trellis decoder using programmable trellis parameters
View Patent ↗A programmable decoder includes at least one programming input for a plurality of programmable, reduced state trellis parameters. A programmable device is connected to the at least one programming input and implements a Reduced-State Sequence Estimation (RSSE) decoder comprising at least one reduced-state trellis structure based upon the plurality of programmable reduced-state trellis parameters, including one of at least the number of super-states, the number of full-states, the number of branches per super-state, a reverse super-state trellis table, a decoder super-state survivor as a full-state, a forward full-state table, a full-state to super-state mapping table, a decoder super-state path metric and decoder super-state traceback array.
1. A programmable decoder comprising:
at least one programming input for a plurality of programmable reduced-state trellis parameters; and
a programmable device connected to the at least one programming input and implementing a reduced-state sequence estimation (RSSE) decoder comprising at least one reduced-state trellis structure based upon the plurality of programmable reduced-state trellis parameters that is comprised of one of at least the number of super-states, the number of full-states, the number of branches per super-state, a reverse super-state trellis table, a decoder super-state survivor as a full-state, a forward full-state table, a full-state to super-state mapping table, decoder super-state path metric and decoder super-state traceback array.
2. The programmable decoder according to claim 1 , wherein all programmable parameters are integers.
3. The programmable decoder according to claim 1 , wherein the decoder state structure is comprised of a path metric per super-state, a traceback array per super-state, and a survivor full-state per super-state.
4. The programmable decoder according to claim 1 , wherein the decoder supports demodulation of waveforms with memory and/or having a forward error correction (FEC) code.
5. The programmable decoder according to claim 1 , wherein the decoder supports demodulation of continuous phase modulation (CPM), IS1 channels and trellis coded modulation (TCM).
6. The programmable decoder according to claim 1 , wherein the reduced-state trellis structure is formed from an Ungerboeck-Style set-partitioning algorithm.
7. The programmable decoder according to claim 1 , wherein the reduced-state trellis structure is formed from a two-state Svensson-Style structure.
8. The programmable decoder according to claim 1 , wherein the reduced-state trellis structure is formed from a M-state Svensson-style structure.
9. The programmable decoder according to claim 1 , wherein the RSSE decoder comprises a decoder state structure that contains path metrics, full decoder state used for decision feedback and traceback array.
10. The programmable decoder according to claim 9 , wherein the RSSE decoder further comprises a Forward full-state Trellis structure operative for indicating which full decoder state from a decision feedback is connected to a next full decoder state for any given symbol.
11. The programmable decoder according to claim 1 , wherein the programmable device comprises a field programmable gate array (FPGA) or Digital Signal Processor (DSP).
12. The programmable decoder according to claim 1 , and further comprising at least one output connected to said programmable device for outputting decoded bits with multiple bits per output.
13. The programmable decoder according to claim 12 , wherein the at least one output is operative for outputting a full traceback of all decoded bits for the winning super-state.
14. The programmable decoder according to claim 1 , and further comprising at least one output connected to the programmable device for outputting a winning state for a current best path metric.
15. A programmable decoder comprising:
at least one programming input for a plurality of programmable reduced-state trellis parameters, including a reduced-state programming input representing combined full-states for a reduced-state trellis; and
a programmable device connected to the at least one programming input and reduced-state programming input and implementing a reduced-state sequence estimation (RSSE) decoder comprising at least one reduced-state trellis structure based upon the plurality of programmable reduced-state trellis parameters that comprise one of at least the number of super-states, the number of full-states, the number of branches per super-state, a reverse super-state trellis table, a decoder super-state survivor as a full-state, a forward full-state table, a full-state to super-state mapping table, decoder super-state path metric and decoder super-state traceback array.
16. The programmable decoder according to claim 15 , wherein the decoder supporting demodulation of waveforms with memory and/or having a forward error correction (FEC) code.
17. The programmable decoder according to claim 15 , wherein the reduced-state trellis structure is formed from an Ungerboeck-Style set-partitioning algorithm.
18. The programmable decoder according to claim 15 , wherein the reduced-state trellis structure is formed from a two-state Svensson-Style structure.
19. The programmable decoder according to claim 15 , wherein the reduced-state trellis structure is formed from a M-state Svensson-style structure.
20. The programmable decoder according to claim 15 , wherein the RSSE decoder further comprises a decoder state structure that contains path metrics, full decoder state used for decision feedback and traceback array.
21. The programmable decoder according to claim 15 , wherein the RSSE decoder further comprises a Forward full-state Trellis structure operative for indicating which full decoder state from a decision feedback is connected to a next full decoder state for any given symbol.
22. The programmable decoder according to claim 15 , and further comprising at least one output connected to the programmable device for outputting a winning super-state or full-state for a current best path metric.
23. A method of implementing a programmable decoder, comprising:
providing a programming device to implement a reduced-state sequence estimation (RSSE) decoder comprising at least one reduced-state trellis structure based upon the plurality of programmable reduced-state trellis parameters that comprise one of at least the number of super-states, the number of full-states, the number of branches per super-state, a reverse super-state trellis table, a decoder super-state survivor as a full-state, a forward full-state table, a full-state to super-state mapping table, decoder super-state path metric and decoder super-state traceback array; and programming the plurality of programmable reduced-state trellis parameters via at least one programming input connected to the programmable device.
24. A method according to claim 23 , which further comprises demodulating within the programming device waveforms with memory and/or having a forward error correction (FEC) code.
25. A method according to claim 23 , which further comprises demodulating within the programming device continuous phase modulation (CPM), IS1 channels and trellis coded modulation (TCM).
26. A method according to claim 23 , which further comprises forming an Ungerboeck-Style set-partitioning trellis structure.
27. A method according to claim 23 , which further comprises forming a two-state Svensson-Style trellis structure.
28. A method according to claim 23 , which further comprises forming a M-state Svensson-style trellis structure.
29. A method according to claim 23 , which further comprises forming a decoder state structure that contains path metrics and a full decoder state used for decision feedback.
30. A method according to claim 29 , which further comprises forming a Forward Trellis structure operative for indicating which full decoder state from a decision feedback is connected to a next full decoder state for any given bit.