Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same
View Patent ↗A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.
1. A thin film transistor array panel, comprising:
a gate line formed on a substrate including a first conductive layer and a second conductive layer on the first conductive layer;
a storage electrode formed on the substrate and separated from the gate line;
a first insulating layer formed on the gate line and the storage electrode;
a semiconductor layer formed on the first insulating layer;
a data line and a drain electrode formed at least partially on the semiconductor layer;
a conductor formed on the first insulating layer, overlapping the storage electrode, and separated from the drain-electrode;
a second insulating layer formed on the data line, the drain electrode and the conductor and having a contact hole exposing the conductor; and
a pixel electrode formed on the second insulating layer, overlapping the data line, and electrically connected to the drain electrode.
2. A thin film transistor array panel of claim 1 , wherein the conductor is made of the same material as the data line.
3. A thin film transistor array panel of claim 1 , wherein the semiconductor layer has the same layout as the corresponding data line, the drain electrode and the conductor except for a channel part of a thin film transistor.
4. A thin film transistor array panel of claim 1 , wherein the data line is overlapped the pixel electrode.
5. A thin film transistor array panel of claim 1 , wherein the gate line comprises a gate pad that is connected to and receives scanning signals from an external circuit.
6. A thin film transistor array panel of claim 5 , wherein the gate pad comprises a single-layered structure.
7. A thin film transistor array panel of claim 5 , wherein the first insulating layer has a first contact hole exposing the gate pad and the second insulating layer has a second contact hole exposing the gate pad, the first contact hole and the second contact hole have the same form in a plan view.