Method for determining and method for compensating a characteristic of an A/D converter, circuit arrangement for determining such a characteristic, and A/D converter circuit arrangement
View Patent ↗An analog-to-digital converter circuit arrangement comprising an analog-to-digital converter that receives an analog input signal and provides a digital output signal. A correction device that corrects the digital output signal using multidimensional correction coefficients indicative of a characteristic of the analog-to-digital converter to be compensated for, and provides a corrected digital output signal indicative thereof.
1. A method for determining a characteristic of an analog-to-digital converter, comprising the steps of:
applying a test signal having a plurality of frequency components to an analog-to-digital converter to generate a digital output signal; and
comparing the digital output signal against a known test output signal, and depending on the result of the comparison generating a multidimensional correction coefficient for correction of signals being converted by the analog-to-digital converter.
2. The method of claim 1 , further comprising notch filtering at several test signal frequencies (f 1 , f 2 ) to generate the multidimensional correction coefficients.
3. The method of claim 1 , wherein the test signal (a(f 1 +f 2 )) to determine the multidimensional correction coefficient is formed from at least two superimposed input signals of different test signal frequencies (f 1 , f 2 ).
4. A method for compensating a characteristic of an analog-to-digital converter, comprising:
digitizing an analog input signal to provide a digital output signal; and
compensating the digital output signal with a multidimensional correction coefficient to provide a compensated digital output signal.
5. The method of claim 4 , wherein for every further dimension of the at least one multidimensional coefficient (sc, dc), one considers an additional input value (z −1 ) lying further in the past.
6. The method of claim 4 , wherein the multidimensional correction coefficient comprises a static coefficient and at least one dynamic coefficient.
7. The method of claim 6 , wherein a repetition rate of the dynamic coefficient is taken into account during the step of compensating.
8. The method of claim 7 , wherein the repetition rate is set based upon a folding structure of the analog-to-digital converter.
9. The method of claim 7 , wherein the rate of repetition of a number of correction fields is set accordingly through a modulation of the analog-to-digital converter.
10. The method of claim 4 , further comprising notch filtering at a plurality of test frequency values to determine the multidimensional correction coefficients.
11. The method of claim 4 , wherein a notch filtering is used, wherein parameters are adjusted to reduce harmonics that fall in regions around test signal frequencies (f 1 , f 2 ) that were used to determine the at least one multidimensional coefficient.
12. A circuit arrangement for determining a characteristic of an analog-to-digital converter, comprising:
an analog-to-digital converter that receives a test signal;
a coefficient determining device for determining at least one multidimensional correction coefficient by comparing a digital output signal from the analog-to-digital converter with a desired state of the digital output signal; and
a storage device for storing the at least one correction coefficient, wherein the coefficient determining device determines the at least one multidimensional coefficient with at least two dimensions as the basis for correction values for the analog-to-digital converter.
13. An analog-to-digital converter circuit arrangement, comprising:
an analog-to-digital converter that receives an analog input signal and provides a digital output signal and;
a correction device that corrects the digital output signal using a multidimensional correction coefficient indicative of a characteristic of the analog-to-digital converter to be compensated for, and provides a corrected digital output signal indicative thereof.
14. The circuit arrangement of claim 13 , wherein the correction device provides a static correction value and a dynamic correction value, wherein the correction device subtracts both the static and dynamic correction values from the digital output value to provide the corrected digital output signal.
15. The circuit arrangement of claim 14 wherein the correction device comprises a modulo unit, depending on a repetition rate of a converter structure of the analog-to-digital converter.
16. The circuit arrangement of claim 14 , wherein the digital output value is input to a first subtraction unit and to a delay unit that provides a delayed digital output value, and the delayed digital output value is also provided to the first subtraction unit that provides a difference signal, indicative of the difference between the digital output value and the delayed digital output value, to the correction device for generating the dynamic correction value.
17. The circuit arrangement of claim 16 , further comprising a notch filter for filtering the digital output value in consideration of test signal frequencies (f 1 , f 2 ) to provide a notch filtered signal that is input to the correction device to generate the multidimensional correction coefficient.