Semiconductor integrated circuit apparatus and electronic apparatus
View Patent ↗A semiconductor integrated circuit apparatus and an electronic apparatus having a power control function configured from power control MOS transistors such that leakage current and on-resistance at the time of cut-off is sufficiently small in actual use. The semiconductor integrated circuit apparatus includes a CMOS logic circuit, a first pseudo power supply line connected to a high potential side power supply terminal of the CMOS logic circuit, a second pseudo power supply line connected to a low potential side power supply terminal of the CMOS logic circuit, and a power control NchMOS transistor connected across the second pseudo power supply line and a low potential side power supply line, with the substrate and gate of the power control NchMOS transistor being electrically connected. The gate and the substrate may also be connected via a current limiter utilizing a source follower of a depletion type NchMOS transistor.
1. A semiconductor integrated circuit apparatus, comprising:
a logic circuit having a plurality of NchMIS transistors and a plurality of PchMIS transistors;
a first pseudo power supply line connected to a high potential side power supply terminal section of the logic circuit;
a second pseudo power supply line connected to a low potential side power supply terminal section of the logic circuit; and
a first NchMIS transistor formed on a silicon substrate of a silicon-on-insulator structure, wherein:
the second pseudo power supply line is connected to a drain of the first NchMIS transistor;
a low potential side power supply line is connected to a source of the first NchMIS transistor;
a gate of the first NchMIS transistor and the substrate are connected through a current limiter;
an absolute value of a threshold voltage of the first NchMIS transistor does not exceed an absolute value of a threshold voltage of the MIS transistors of the logic circuit, or the first NchMIS transistor is a depletion type; and
a low level of a signal applied to the gate of the first NchMIS transistor is lower than a potential of the low potential side power supply line.
2. The semiconductor integrated circuit apparatus according to claim 1 , wherein the current limiter comprises a bi-directional source follower.
3. The semiconductor integrated circuit apparatus according to claim 1 , wherein the current limiter comprises an analogue switch.
4. An electronic apparatus comprising a semiconductor integrated circuit apparatus having a power supply apparatus and a power control function of the power supply apparatus, wherein the semiconductor integrated circuit apparatus comprises a semiconductor integrated circuit apparatus according to claim 1 .
5. A semiconductor integrated circuit apparatus, comprising:
a logic circuit having a plurality of NchMIS transistors and a plurality of PchMIS transistors;
a first pseudo power supply line coupled to a high potential side power supply terminal section of the logic circuit;
a second pseudo power supply line coupled to a low potential side power supply terminal section of the logic circuit; and
a first PchMIS transistor formed on a silicon substrate of a silicon-on-insulator structure, wherein:
the first pseudo power supply line is connected to a drain of the first PchMIS transistor;
a high potential side power supply line is connected to a source of the first PchMIS transistor;
a gate of the first PchMIS transistor and the substrate are connected through a current limiter;
an absolute value of a threshold voltage of the first PchMIS transistor does not exceed an absolute value of a threshold voltage of the MIS transistors of the logic circuit, or the first PchMIS transistor is a depletion type; and
a high level of a signal applied to the gate of the first PchMIS transistor is higher than a potential of the high potential side power supply line.
6. The semiconductor integrated circuit apparatus according to claim 5 , wherein the current limiter comprises a bi-directional source follower.
7. The semiconductor integrated circuit apparatus according to claim 5 , wherein the current limiter comprises an analogue switch.
8. A semiconductor integrated circuit apparatus, comprising:
a logic circuit having a plurality of NchMIS transistors and a plurality of PchMIS transistors;
a first pseudo power supply line coupled to a high potential side power supply terminal section of the logic circuit;
a second pseudo power supply line coupled to a low potential side power supply terminal section of the logic circuit;
a first NchMIS transistor which has a threshold voltage which does not exceed an absolute value of a threshold voltage of the MIS transistors of the logic circuit or which is a depletion type; and
a second NchMIS transistor which has a threshold voltage which does not exceed the absolute value of the threshold voltage of the MIS transistors of the logic circuit or which is the depletion type, wherein:
a source of the second NchMIS transistor is connected to a drain of the first NchMIS transistor;
the second pseudo power supply line is connected to a drain of the second NchMIS transistor;
a low potential side power supply line is connected to a source of the first NchMIS transistor; and
a substrate of the first NchMIS transistor and a substrate of the second NchMIS transistor are coupled to a gate of the second NchMIS transistor.
9. The semiconductor integrated circuit apparatus according to claim 8 , wherein the substrate of the first NchMIS transistor and the substrate of the second NchMIS transistor are connected to the gate of the second NchMIS transistor through a current limiter.
10. A semiconductor integrated circuit apparatus, comprising:
a logic circuit having a plurality of NchMIS transistors and a plurality of PchMIS transistors;
a first pseudo power supply line connected to a high potential side power supply terminal section of the logic circuit;
a second pseudo power supply line connected to a low potential side power supply terminal section of the logic circuit;
a first NchMIS transistor which has a threshold voltage which does not exceed an absolute value of a threshold voltage of the MIS transistors of the logic circuit or which is a depletion type; and
a second NchMIS transistor which has a threshold voltage which does not exceed the absolute value of the threshold voltage of the MIS transistors of the logic circuit or which is the depletion type, wherein:
a source of the second NchMIS transistor is connected to a drain of the first NchMIS transistor;
the second pseudo power supply line is connected to a drain of the second NchMIS transistor;
a low potential side power supply line is connected to a source of the first NchMIS transistor; and
a substrate of the first NchMIS transistor and a substrate of the second NchMIS transistor are coupled to a gate of the first NchMIS transistor.
11. The semiconductor integrated circuit apparatus according to claim 10 , wherein the substrate of the first NchMIS transistor and the substrate of the second NchMIS transistor are connected to the gate of the first NchMIS transistor through a current limiter.
12. A semiconductor integrated circuit apparatus, comprising:
a logic circuit having a plurality of NchMIS transistors and a plurality of PchMIS transistors;
a first pseudo power supply line connected to a high potential side power supply terminal section of the logic circuit;
a second pseudo power supply line connected to a low potential side power supply terminal section of the logic circuit;
a first PchMIS transistor which has a threshold voltage which does not exceed an absolute value of a threshold voltage of the MIS transistors of the logic circuit or which is a depletion type; and
a second PchMIS transistor which has a threshold voltage which does not exceed the absolute value of the threshold voltage of the MIS transistors of the logic circuit or which is the depletion type, wherein
a source of the second PchMIS transistor is connected to a drain of the first PchMIS transistor;
the first pseudo power supply line is connected to a drain of the second PchMIS transistor;
a high potential side power supply line is connected to a source of the first PchMIS transistor; and
a substrate of the first PchMIS transistor and a substrate of the second PchMIS transistor are coupled to a gate of the second PchMIS transistor.
13. The semiconductor integrated circuit apparatus according to claim 12 , wherein the substrate of the first PchMIS transistor and the substrate of the second PchMIS transistor are connected to the gate of the second PchMIS transistor through a current limiter.
14. A semiconductor integrated circuit apparatus, comprising:
a logic circuit having a plurality of NchMIS transistors and a plurality of PchMIS transistors;
a first pseudo power supply line connected to a high potential side power supply terminal section of the logic circuit;
a second pseudo power supply line connected to a low potential side power supply terminal section of the logic circuit;
a first PchMIS transistor which has a threshold voltage which does not exceed an absolute value of a threshold voltage of the MIS transistors of the logic circuit or which is a depletion type; and
a second PchMIS transistor which has a threshold voltage which does not exceed the absolute value of the threshold voltage of the MIS transistors of the logic circuit or which is the depletion type, wherein:
a source of the second PchMIS transistor is connected to a drain of the first PchMIS transistor;
the first pseudo power supply line is connected to a drain of the second PchMIS transistor;
a high potential side power supply line is connected to a source of the first PchMIS transistor; and
a substrate of the first PchMIS transistor and a substrate of the second PchMIS transistor are coupled to a gate of the first PchMIS transistor.
15. The semiconductor integrated circuit apparatus according to claim 14 , wherein the substrate of the first PchMIS transistor and the substrate of the second PchMIS transistor are connected to the gate of the first PchMIS transistor through a current limiter.