Multiphase addressing method for transferring address information
View Patent ↗A method of performing a burst read access at a memory device using a multiplexed data/address bus and a control signal including transferring a first portion of address information in a first phase via the multiplexed data/address bus to the memory device; transferring second portion of address information in a second phase via a multiplexed data/address bus to the memory device; transferring a series of data words from the memory via the multiplexed data/address bus; toggling the state of the control signal at the memory device as each data word is transferred; and suspending the transfer of the series of data words from the memory via the multiplexed data/address bus and the toggling of the state of the control signal.
1. A method of strobing and pacing data transfer between a controller device and a target device using a control signal, comprising:
strobing the transfer of a data word over a data bus from the target device to the controller device by changing as the data word is transferred the state of a signal line, in response to a state change of an external clock, to provide the control signal wherein the signal line is distinct from the data bus and the external clock; and
pacing an on-going transfer of data words from the target device to the controller device by disabling a state change of the signal line without disabling ongoing state changes of the external clock, wherein disabling a state change in the signal line can occur while the signal line is in any state.
2. A method as claimed in claim 1 , wherein the target device is configured to control the state of the signal line.
3. A method as claimed in claim 1 , wherein the method comprises, during a burst read, strobing the transfer of a series of data words from the target device to the controller device by changing the state of the signal line as each data word is transferred and pacing the transfer of the series of data words from the target device to the controller device by disabling state change of the signal line.
4. A method as claimed in claim 1 , wherein the method comprises, during a burst write, pacing the transfer of data words from the controller device to the target device by changing the state of the signal line at the target device.
5. A target device configured to transfer data between a controller device and the target device, the target device comprising:
an interface comprising a data bus configured to transfer data between the target device and the controller device, a signal line configured to provide a control signal to the controller device and an external clock signal line, wherein the signal line is distinct from the data bus and the external clock signal line; and
a strobe mechanism configured to strobe the transfer of data to the controller device over the data bus by changing the state of the signal line, in response to a state change of the external clock signal line, with each data word provided to the bus and a flow control mechanism configured to pace an on-going transfer of data to the controller device by maintaining the state of the signal line without ongoing changes of the external clock signal line being disabled, wherein the flow control mechanism is configured to maintain the state of the signal line in any state.
6. A target device as claimed in claim 5 , wherein the bus is a multiplexed data/address bus.
7. A target device as claimed in claim 5 , wherein the flow control mechanism is additionally configured to pace the transfer of data from the controller by changing the state of the signal line.
8. A target device as claimed in claim 5 , configured to operate as a memory device.
9. A target device as claimed in claim 5 , wherein pacing an on-going transfer of data words from the target device to the controller device is achieved by disabling a state change of the signal line.
10. A controller device configured to transfer data between the controller device and a target device, the controller device comprising:
an interface comprising a data bus configured to transfer data between the target device and the controller device, a signal line configured to receive a control signal from the target device and an external clock signal line, wherein the signal line is distinct from the data bus and the external clock signal line; and
a flow control mechanism configured to latch a data word provided on the bus by the target device during an on-going transfer of data words only when the state of the signal line changes, wherein the state of the signal line changes in response to a state change of the external clock signal line, and wherein the flow control mechanism is configured not to latch a data word if the state of the signal line is maintained in any state without ongoing state changes of the external clock signal line being disabled.
11. A controller device as claimed in claim 10 , wherein the bus is a multiplexed data/address bus.
12. A controller device as claimed in claim 10 , wherein the flow control mechanism is configured to suspend the transfer of data to the target device via the bus when the state of the signal line changes.
13. A method of strobing and pacing data transfer between a controller device and a target device using a control signal, comprising:
strobing a data transfer from the target device to the controller device over a data bus by toggling only with each data transfer the state of a signal line, in response to a state change of an external clock, to provide the control signal wherein a data word is not transferred if the state of the signal line is maintained in any state and without disabling ongoing state changes of the external clock and wherein the signal line is distinct from the data bus and the external clock; and
pacing an on-going data transfer from the controller device to the target device by changing the state of the signal line.
14. A method of performing a burst read access at a memory device using a multiplexed data/address bus and a control signal comprising:
transferring a first portion of address information in a first phase via the multiplexed data/address bus to the memory device;
transferring a second portion of address information in a second phase via the multiplexed data/address bus to the memory device;
transferring a series of data words from the memory device via the multiplexed data/address bus;
toggling only as each data word is transferred the state of a signal line, in response to a state change of an external clock, to provide the control signal at the memory device wherein the signal line is distinct from the data bus and the external clock; and
suspending an on-going transfer of the series of data words from the memory device via the multiplexed data/address bus and suspending the toggling of the state of the signal line without disabling ongoing state changes of the external clock, by maintaining the signal line in any state.