Apparatus for receiving differential signal using a differential amplifier
The invention relates to a receiver for a differential data bus with two resistive branches ( 1, 2, 3; 4, 5, 6 ), with a differential amplifier with two transistors ( 9, 10 ), with a resistor ( 13 ), and with a control logic ( 16 ) that controls a switch ( 15 ) with which a current from a current source ( 14 ) is switchable to either side of the resistor ( 13 ), which resistor couples the two transistors ( 9, 10 ), and with two operational amplifiers ( 17, 18 ) which are coupled to the two transistors ( 9,10 ) of the differential amplifier with opposite poles, in which receiver the control logic detects from the output signals of the two operational amplifiers ( 17,18 ) whether a “0” or a “1” is expected on the bus and which receiver sets the switch ( 25 ) accordingly so that a comparison with the received bus signal is made.
1. Receiver for a differential data bus, the data bus having two bus lines, with two resistive branches with a differential amplifier with two transistors, each said transistor having an emitter and a collector, with a resistor and with a control logic that controls a switch with which a current from a current source is switchable to either side of the resistor which resistor couples the two transistors and with two operational amplifiers, each said operation amplifier having an output signal, which are coupled to the two transistors of the differential amplifier with opposite poles, in which receiver the control logic detects from the output signals of the two operational amplifiers whether a value “0” or a value “1” is expected on the bus and which receiver sets the switch accordingly so that a comparison with the received bus signal is made.
2. Receiver as claimed in claim 1 , characterized in that the two bus lines are coupled to the emitters of the two transistors that the collector of a first transistor of the two transistors is coupled to a negative input of a first comparator and to a positive input of a second comparator, that the collector of a second transistor of the two transistors is coupled to a positive input of the first comparator and to a negative input of the second comparator, and that upon reception of a falling edge on the line of the bus that is coupled to the first transistor the potential of the collector of the second transistor goes down and that of the collector of the first transistor goes up, so that the output signal of the first comparator goes down and that of the second comparator goes up, which causes the control logic to switch the switch to a second position, in which the current source is coupled to the connection between the emitter of the second transistor and the resistor and upon reception of a falling edge on the line of the bus that is coupled to the second transistor the potential of the collector of the second transistor goes up and that of the collector of the first transistor goes down, so that the output signal of the first comparator goes up and that of the second comparator goes down, which causes the control logic to switch the switch to the first position, in which the current is coupled to the connection between the emitter of the first transistor and the resistor.
3. Receiver as claimed in claim 2 , characterized in that the switch is set to the first position when the bus lines are idle.
4. Receiver as claimed in claim 1 , characterized in that the data bus is a bus according to the FlexRay standard.