Granted Patent B2

US 7,842,972 · App. 11/632,670 · Granted Nov 30, 2010

Abstract

Claims (24)

1. A pseudormorphic˜high-electron-mobility-transistor (PHEMT), comprising:

a substrate;

a low-temperature-grown (LTG) GaAs gate-insulator layer disposed on the substrate wherein said LTG GaAs gate-insulator-layer has thickness in the range of approximately 200A and 1000A;

a gate electrode disposed on the LTG GaAs gate-insulator layer;

a channel layer disposed between the substrate and the LTG GaAs gate-insulator-layer;

a first spacer layer disposed between a GaAs layer and the LTG GaAs gate-insulator layer;

the GaAs layer disposed between the channel layer and the LTG GaAs gate-insulator layer wherein said GaAs layer is doped with silicon and has a thickness in the range of approximately 100A to 500A;

wherein the first spacer layer comprises an AlAs layer having a thickness in the range of approximately 25A to 100A;

and further comprising a: LTG GaAs buffer layer disposed between the substrate and the channel layer;

and wherein the LTG GaAs buffer layer has a thickness in the range of approximately 0.5 um to 1.0 um, and further comprising a second spacer layer disposed between the LTG GaAs buffer layer and the channel layer;

and wherein the second spacer layer comprises:

an AlAs layer;

an AlGaAs layer; and

a super lattice layer disposed between the AlAs and AlGaAs layers;

wherein the AlAs layer is doped with silicon and has a thickness of approximately 100A;

the super lattice layer comprises a GaAs/AlGaAs layer having a thickness in the range of approximately 200A to 800A; the AlGaAs layer is doped with silicon and has a thickness of approximately 50A.

2. The PHEMT of claim 1 , wherein the channel layer comprises an InGaAs layer having a thickness in the range of approximately 90 Å to 120 Å.

3. The PHEMT of claim 1 , further comprising:

a channel layer disposed between the substrate and the LTG GaAs gate-insulating layer;

a gate electrode;

a source electrode;

a drain electrode;

a first N + GaAs contact disposed between the source electrode and the channel layer and not under the gate electrode; and

a second N + GaAs contact disposed between the drain electrode and the channel layers and not under the gate electrode.

Assignments (10)