IP Library Granted Patent US 8,089,113
Granted Patent B2
US 8,089,113 · App. 11/633,929 · Granted Jan 3, 2012

Damascene metal-insulator-metal (MIM) device

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Quick Facts
Patent No.
US 8,089,113
App. No.
11/633,929
Granted
Jan 3, 2012
Kind
B2
Abstract

The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.

Claims (55)

1. A method of fabricating a memory device comprising:

providing a dielectric layer;

providing an opening in the dielectric layer;

providing a first conductive body in the opening;

providing a switching body in the opening; and

providing a second conductive body in the opening wherein a conductive glue is formed above the second conductive body.

2. The method of claim 1 wherein the switching body contacts the first conductive body, and the second conductive body contacts the switching body.

3. The method of claim 1 and further comprising providing a third conductive body in the opening.

4. The method of claim 3 wherein the third conductive body contacts the second conductive body.

5. The method of claim 4 and further comprising said memory device incorporated in a system.

6. The method of claim 5 wherein the system is selected from the group consisting of a hand-held device, a vehicle, and a computer.

7. A method of fabricating a memory device comprising:

providing a first dielectric layer;

providing an opening in the first dielectric layer;

providing a first conductive body in the opening in the first dielectric layer;

providing a second dielectric layer;

providing an opening in the second dielectric layer;

providing a switching body in the opening in the second dielectric layer; and

providing a second conductive body in the opening in the second dielectric layer wherein a conductive glue is formed above the second conductive body.

8. The method of claim 7 wherein the switching body contacts the first conductive body, and the second conductive body contacts the switching body.

9. A method of fabricating a memory device comprising:

providing a dielectric layer;

providing an opening in the dielectric layer;

providing a first conductive layer on the dielectric layer and in the opening;

providing a layer of switching material on the first conductive layer and in the opening;

providing a second conductive layer on the layer of switching material and in the opening wherein a conductive glue is formed above the second conductive layer; and

removing portions of the first conductive layer, layer of switching material and second conductive layer from over the dielectric layer so that remaining portions of the first conductive layer, layer of switching material and second conductive layer are within the opening.

10. The method of claim 9 and further comprising providing a third conductive layer on the second conductive layer, and removing portions of the first conductive layer, layer of switching material, second conductive layer and third conductive layer from over the dielectric layer so that remaining portions of the first conductive layer, layer of switching material, second conductive layer and third conductive layer are within the opening.

11. The method of claim 10 and further comprising providing an additional dielectric layer over the resulting structure, providing an opening in the additional dielectric layer, and providing an additional conductive layer on the additional dielectric layer and in the opening of the additional dielectric layer and contacting the portion of the third conductive layer in the opening in the first-mentioned dielectric layer.

12. The method of claim 9 and further comprising providing an additional dielectric layer over the resulting structure, providing an opening in the additional dielectric layer, and providing an additional conductive layer on the additional dielectric layer and in the opening of the additional dielectric layer and contacting the portion of the second conductive layer in the opening in the first-mentioned dielectric layer.

13. A method of fabricating a memory device comprising:

providing a first dielectric layer;

providing an opening in the first dielectric layer;

providing a first conductive layer on the first dielectric layer and in the opening in the first dielectric layer;

removing portions of the first conductive layer from over the first dielectric layer so that a remaining portion of the first conductive layer is within the opening in the first dielectric layer;

providing a second dielectric layer on the first dielectric layer;

providing an opening in the second dielectric layer;

providing a layer of switching material on the second dielectric layer and in the opening in the second dielectric layer and on the remaining portion of the first conductive layer;

providing a second conductive layer on the layer of switching material and in the opening in the second dielectric layer wherein a conductive glue is formed above the second conductive layer; and

removing portions of the layer of switching material and second conductive layer from over the second dielectric layer so that remaining portions of the layer of switching material and second conductive layer are within the opening in the second dielectric layer.

14. The method of claim 13 and further comprising providing an additional dielectric layer over the resulting structure, providing an opening in the additional dielectric layer, and providing an additional conductive layer on the additional dielectric layer and in the opening of the additional dielectric layer and contacting the portion of the second conductive layer in the opening in the second dielectric layer.

15. A memory device comprising;

a dielectric layer having an opening;

a first conductive layer in the opening;

a layer of switching material in the opening and on the first conductive layer; and a second conductive layer in the opening and on the layer of switching material wherein a conductive glue is formed above the second conductive layer.

16. The memory device of claim 15 and further comprising a third conductive layer in the opening and on the second conductive layer.

17. The memory device of claim 16 and further comprising an additional dielectric layer on the first-mentioned dielectric layer and having an opening, and an additional conductive layer on the additional dielectric layer and in the opening of the additional dielectric layer and contacting the third conductive layer in the opening in the first dielectric layer.

18. The memory device of claim 15 and further comprising an additional dielectric layer on the first-mentioned dielectric layer and having an opening, and an additional conductive layer on the additional dielectric layer and in the opening of the additional dielectric layer and contacting the second conductive layer in the opening in the first dielectric layer.

19. A memory device comprising;

a first dielectric layer having a opening therein;

a first conductive layer in the opening of the first dielectric layer;

a second dielectric layer on the first dielectric layer and having an opening therein;

a layer of switching material in the opening of the second dielectric layer and on the first conductive layer; and

a second conductive layer in the opening of the second dielectric layer and on the layer of switching material wherein a conductive glue is formed above the second conductive layer.

20. The memory device of claim 19 and further comprising an additional dielectric layer on the second dielectric layer and having an opening, and an additional conductive layer on the additional dielectric layer and in the opening of the additional dielectric layer and contacting the second conductive layer in the opening in the second dielectric layer.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →