Power saving in multi-processor device
View Patent ↗A mobile computing device comprises a first microprocessor having a sleep mode and a wake mode and a second microprocessor configured for wireless communication. A communication port is configured to communicate data from the second processor to the first processor, wherein the second processor is configured to provide a wake signal to the first microprocessor and the first microprocessor is configured to open the communication port in response to the wake signal and to receive data from the second microprocessor through the communication port.
1. A mobile computing device, comprising:
a first microprocessor configured to operate a plurality of applications and having a sleep mode and a wake mode;
a second microprocessor configured to provide wireless communication over a network;
a universal serial bus; and
a universal serial bus controller having on, off and suspend states, the universal serial bus controller coupled to the first microprocessor and configured to provide universal serial bus communication with the second microprocessor, wherein after processing a message on the universal serial bus, the universal serial bus controller is configured to enter the off state while the first microprocessor is in a sleep state; and
a serial communication bus controller coupled to the first microprocessor, the serial communication bus controller having an on state and an off state, wherein the universal serial bus controller is configured to be put in the off state when the serial communication bus controller is in the on state.
2. The mobile computing device of claim 1 , wherein the universal serial bus controller is configured to move from the off to the on state without enumerating.
3. The mobile computing device of claim 1 , wherein the first and second microprocessors are part of a dual core chip.
4. The mobile computing device of claim 1 , wherein the second microprocessor has a sleep mode and a wake mode.
5. The mobile computing device of claim 1 , wherein the second microprocessor is a modem.
6. A mobile computing device comprising:
a first microprocessor configured to operate a plurality of applications and having a sleep mode and a wake mode;
a second microprocessor configured to provide wireless communication over a network;
a universal serial bus; and
first controller means having on, off and suspend states, the first controller means for providing communication between the first microprocessor and the second microprocessor, wherein after processing a message, the first controller means is configured to enter the off state while the first microprocessor is in a sleep state; and
second controller means having an on state and an off state, the second controller means for providing communication between the first microprocessor and the second microprocessor;
wherein the first controller means is configured to be put in the off state when the second controller means is in the on state;
wherein the first controller means is a universal serial bus controller means;
wherein the second controller means is a serial communication bus controller means.
7. The mobile computing device of claim 6 , wherein the first controller means is configured to move from the off state to the on state without enumerating.
8. The mobile computing device of claim 6 , wherein the first and second microprocessors are part of a dual-core integrated circuit.
9. The mobile computing device of claim 6 , wherein the second microprocessor has a sleep mode and a wake mode.
10. The mobile computing device of claim 6 , wherein the second microprocessor is a modem.
11. A method comprising:
processing a message on a universal serial bus using a universal serial bus controller, the universal serial bus controller having on, off and suspend states, the universal serial bus controller coupled to a first microprocessor and configured to provide universal serial bus communication with a second microprocessor;
putting the universal serial bus controller in the off state while the first processor is in a sleep state after processing the message on the universal serial bus; and
putting a serial communication bus controller in an off state when the universal serial bus controller is in the on state, the serial communication bus controller being coupled to the first microprocessor, the serial communication bus controller having an on state and the off state.
12. The method of claim 11 , wherein the first microprocessor is configured to operate a plurality of applications.
13. The method of claim 11 , wherein the second microprocessor is configured to provide wireless communication over a network.
14. The method of claim 11 , wherein the first and second microprocessors are part of a dual core chip.
15. The method of claim 11 , wherein each of the first and second microprocessors has a sleep mode and a wake mode.