Array substrate for liquid crystal display device and fabrication method thereof
View Patent ↗Provided is a liquid crystal display (LCD) device and a fabrication method thereof. An array substrate for the LCD includes a gate line formed on a substrate, and a gate electrode extending from the gate line; a data line intersected with the gate line, wherein the data line is configured with a gate insulating layer, a semiconductor layer and a data metal layer; a pixel electrode formed of a first transparent metal layer at a pixel which is defined by an intersection of the gate line and the data line; a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode by a predetermined distance to expose a channel; and a second transparent metal layer pattern formed on the data line, the source electrode and the drain electrode, wherein the second transparent metal layer connects the drain electrode and the pixel electrode to each other.
1. A method for fabricating an array substrate for a liquid crystal display device, the method comprising:
forming a gate line configured with a first transparent metal layer, a first gate metal layer and a second gate metal layer stacked in sequence, a gate electrode extending from the gate line, and a pixel electrode formed of the first transparent metal layer;
depositing a gate insulating layer, a semiconductor layer and a data metal layer on the substrate;
patterning the gate insulating layer, the semiconductor layer and the data metal layer to form a data line intersected with the gate line, and source and drain electrodes extending from the data line, wherein the source and drain electrodes are connected to each other over the gate electrode;
forming a second transparent metal layer on the substrate;
patterning the second transparent metal layer to form a second transparent metal layer pattern on the data line, the source electrode, the drain electrode and a portion of the pixel electrode; and
etching the data metal layer using the second transparent metal layer pattern as a mask to expose the semiconductor layer between the source and drain electrodes.
2. The method according to claim 1 , wherein the second transparent metal layer is formed to have a cut portion therein over the gate line.
3. The method according to claim 2 , wherein the cut portion exposes the first gate metal layer.
4. The method according to claim 2 , wherein the cut portion is formed at a position where the second transparent metal layer is intersected with the first gate metal layer.
5. The method according to claim 1 , further comprising, after the etching of the data metal layer using the second transparent metal layer pattern as the mask to expose the semiconductor layer between the source and drain electrodes, exposing the semiconductor layer to plasma gas to form an oxide or nitride layer.
6. The method according to claim 1 , further comprising, after the forming of the pixel electrode formed of the first transparent metal layer, crystallizing the first transparent metal layer.
7. The method according to claim 1 , wherein the patterning of the gate insulating layer, the semiconductor layer and the data metal layer to form the data line intersected with the gate line, further comprises forming a partition wall in the vicinity of the second transparent metal layer pattern formed on the pixel electrode, the partition wall having a stacked structure of the gate insulating layer and the semiconductor layer.
8. The method according to claim 1 , wherein the semiconductor layer and the data metal layer are formed in the shape of an island on the gate pad formed at one end of the gate line, the gate insulating layer being interposed between the gate pad and the semiconductor layer.
9. The method according to claim 1 , wherein the second transparent metal layer pattern formed on the pixel electrode electrically connects the drain electrode and the pixel electrode to each other.
10. The method according to claim 1 , wherein the second transparent metal layer and the first transparent metal layer have different etching properties from each other.
11. The method according to claim 1 , wherein the second gate metal layer is etched, in the etching of the data metal layer using the second transparent metal layer pattern as the mask to expose the semiconductor layer between the source and drain electrodes.