Fabrication method for semiconductor device
View Patent ↗A fabrication method for a semiconductor device includes a step of forming a gate insulating film on a semiconductor layer, and a step of forming a first gate electrode layer on the gate insulating film. The fabrication method also includes a step of forming a pocket ion region under the first gate electrode layer, and a step of forming a second gate electrode layer overlaying the first gate electrode layer after forming the pocket ion region.
1. A fabrication method for a semiconductor device, comprising:
forming a gate insulating film on a semiconductor layer;
forming a first gate electrode layer on said gate insulating film;
forming a pocket ion region under said first gate electrode layer;
forming a second gate electrode layer overlaying said first gate electrode layer after forming the pocket ion region;
forming a first side wall on a side face of said first gate electrode layer;
forming a second side wall on a side face of said second gate electrode layer; and
forming an impurity diffusion region on said semiconductor layer after forming said second side wall, wherein said first side wall is formed after said forming a first gate electrode layer and before said forming a second gate electrode layer.
2. The fabrication method according to claim 1 , wherein said pocket ion region is formed by implanting ions in a tilted direction.
3. The fabrication method according to claim 2 , wherein said tilt angle is about 60 degrees with respect to a vertical line.
4. The fabrication method according to claim 2 , wherein said implanting the ions includes implanting arsenic or phosphorus with an impurity concentration of 2×10 15 cm −2 .
5. The fabrication method according to claim 2 , wherein said implanting the ions includes implanting boron or BF 2 with an impurity concentration of 2×10 15 cm −2 .
6. The fabrication method according to claim 1 , wherein said second gate electrode layer is an uppermost layer of a gate electrode of the semiconductor device.
7. The fabrication method according to claim 1 , wherein said semiconductor device is an SOI-MOSFET.
8. The fabrication method according to claim 1 , wherein said first gate electrode layer is about 500 angstroms in thickness and said second gate electrode layer is about 1,000 angstroms in thickness.
9. The fabrication method according to claim 1 , wherein a thickness of said first gate electrode layer is about a half a thickness of said second gate electrode layer.
10. The fabrication method according to claim 1 , wherein said second gate electrode layer is formed on said first gate electrode layer to have a width that is substantially the same as a width of said first gate electrode layer.
11. The fabrication method according to claim 10 , wherein said pocket ion region is formed by implanting ions in a tilted direction.
12. The fabrication method according to claim 10 , wherein said second gate electrode layer is an uppermost layer of a gate electrode of the semiconductor device.
13. The fabrication method according to claim 10 , wherein said semiconductor device is an SOI-MOSFET.
14. The fabrication method according to claim 13 , wherein said tilt angle is about 60 degrees with respect to a vertical line.
15. The fabrication method according to claim 10 , wherein said first gate electrode layer is about 500 angstroms in thickness and said second gate electrode layer is about 1,000 angstroms in thickness.
16. The fabrication method according to claim 10 , wherein a thickness of said first gate electrode layer is about a half a thickness of said second gate electrode layer.
17. The fabrication method according to claim 10 , wherein said implanting the ions includes implanting arsenic or phosphorus with an impurity concentration of 2×10 15 cm −2 .
18. The fabrication method according to claim 10 , wherein said implanting the ions includes implanting boron or BF 2 with an impurity concentration of for 2×10 15 cm −2 .