Semiconductor memory device
View Patent ↗A basic cell comprises a memory cell capable of retaining data having at least a binary value, a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line, and a second selecting transistor connected between the first terminal of the memory cell and the M+1th bit line. Agate of the first selecting transistor is connected to the 2·N−1th selecting line, and a gate of the second selecting transistor is connected to the 2·Nth selecting line.
1. A semiconductor memory device comprising a memory cell array comprising a single or a plurality of basic cells, and selecting lines, bit lines and word lines respectively provided for designating the basic cells, wherein
the basic cell comprises, provided that N and M are respectively integers of at least one:
a memory cell capable of retaining data having at least a binary value;
a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line; and
a second selecting transistor connected between the first terminal of the memory cell and the M+1th bit line, wherein
a gate of the first selecting transistor is connected to the 2·N−1th selecting line, and
a gate of the second selecting transistor is connected to the 2·Nth selecting line,
each of the plurality of bit lines is shared by memory cells arranged on each side of the each bit line.
2. The semiconductor memory device as claimed in claim 1 , further comprising a selecting transistor TL [n+1, m] and a selecting transistor TR [n, m]which are coupled to a common selecting line, where (n≧0, m≧0).
3. The semiconductor memory device as claimed in claim 1 , further comprising a reader for selecting one of the first and second selecting transistors in accordance with a selected address and reading data of the memory cell from the Mth bit line or the M+1th bit line.
4. The semiconductor memory device as claimed in claim 1 , wherein the first selecting transistor and the second selecting transistor are switched over based on a result of comparison of an inputted address to an address previously inputted.
5. semiconductor memory device as claimed in claim 4 , wherein the first selecting transistor and the second transistor are switched over when an inputted bit line selecting address and the bit line selecting address previously inputted are coincident with each other provided that the address to be compared is regarded as the bit line selecting address, or when the two selecting bit lines designated by the bit line selecting addresses are both even-numbered or odd-numbered.