Method and system for instruction set simulation with concurrent attachment of multiple debuggers
View Patent ↗An ISS (instruction set simulator) debugging method. The method includes executing a plurality of instructions of an ISS (instruction set simulator). For each instruction, an ISS simulation state is synchronized to a simulation time when the execution of the instruction is finished. At least two debugger components are executed in conjunction with the execution of the ISS, wherein the debugger components are each coupled to control the ISS.
1. A computer implemented method for ISS (instruction set simulator) debugging, the method comprising:
executing an ISS (instruction set simulator) that runs a simulation of a multicore target device;
executing a plurality of debugger components in conjunction with the execution of the ISS, each of the plurality of debugger components coupled to independently control the ISS via the ISS run control component;
executing the plurality of debugger components in a run mode; and
responsive to a debugger component from the plurality of debugger components transitioning from the run mode to a stop mode:
setting a Boolean configuration flag based on the debugger component transitioning to stop mode, and
completely stopping, by the ISS run control component, the ISS and the simulation of the multicore device based on the Boolean configuration flag, while the ISS and the simulation of the multicore device are completely stopped, at least a different debugger component from the plurality of debugger components continuing to execute in the run mode.
2. The method of claim 1 , wherein each debugger component independently sets breakpoints within the ISS.
3. The method of claim 1 , wherein each debugger component independently sets watchpoints within the ISS.
4. The method of claim 1 , wherein the plurality of debugger components communicate with the ISS via the ISS run control component, and the ISS run control component preventing run-time interference between the plurality of debugger components.
5. The method of claim 1 , wherein each debugger component communicates with the ISS run control component via an ISS stopper.
6. A non-transitory computer readable storage medium, the computer readable storage medium having computer readable instructions therein, which when executed by a processor of a computer system causes the performance of steps comprising:
executing an ISS (instruction set simulator) that runs a simulation of a multicore target device;
executing a plurality of debugger components in conjunction with the execution of the ISS, each of the plurality of debugger components coupled to independently control the ISS via the ISS run control component;
executing the plurality of debugger components in a run mode; and
responsive to a debugger component from the plurality of debugger components transitioning from the run mode to a stop mode:
setting a Boolean configuration flag based on the debugger component transitioning to stop mode, and
completely stopping, by the ISS run control component, the ISS and the simulation of the multicore device based on the Boolean configuration flag, while the ISS and the simulation of the multicore device are completely stopped, at least a different debugger component from the plurality of debugger components continuing to execute in the run mode.
7. The computer readable storage medium of claim 6 , wherein each debugger component independently sets breakpoints within the ISS.
8. The computer readable storage medium of claim 6 , wherein each debugger component independently sets watchpoints within the ISS.
9. The computer readable storage medium of claim 6 , wherein the plurality of debugger components communicate with the ISS via the ISS run control component, and the ISS run control component preventing run-time interference between the plurality of debugger components.
10. The computer readable storage medium of claim 6 , wherein each debugger component communicates with the ISS run control component via an ISS stopper.
11. A system for ISS (instruction set simulator) debugging, the system comprising:
a computer processor; and
a non-transitory computer-readable storage medium having computer program instructions that when executed by a computer processor cause the performance of steps comprising:
executing an ISS (instruction set simulator) that runs a simulation of a multicore target device;
executing a plurality of debugger components in conjunction with the execution of the ISS, each of the plurality of debugger components coupled to independently control the ISS via the ISS run control component;
executing the plurality of debugger components in a run mode; and
responsive to a debugger component from the plurality of debugger components transitioning from the run mode to a stop mode:
setting a Boolean configuration flag based on the debugger component transitioning to stop mode, and
completely stopping, by the ISS run control component, the ISS and the simulation of the multicore device based on the Boolean configuration flag, while the ISS and the simulation of the multicore device are completely stopped, at least a different debugger component from the plurality of debugger components continuing to execute in the run mode.
12. The system of claim 11 , wherein each debugger component independently sets breakpoints within the ISS.
13. The system of claim 11 , wherein each debugger component independently sets watchpoints within the ISS.
14. The system of claim 11 , wherein each debugger component communicates with the ISS run control component via an ISS stopper.