Semiconductor integrated circuit device
View Patent ↗A semiconductor integrated circuit device has an SOI substrate comprising an insulating film laminated on a semiconductor support substrate and a semiconductor thin film laminated on the insulating film. A first N-channel MOS transistor, a first P-channel MOS transistor, and a resistor are each disposed on the semiconductor thin film. A second N-channel MOS transistor serving as an electrostatic discharge (ESD) protection element is disposed on a surface of the semiconductor support substrate that is exposed by removing a part of the semiconductor thin film and a part of the insulating film. The second N-channel MOS transistor has a gate electrode, a source region and a drain region surrounding the source region through the gate electrode to maintain a constant distance between the drain region and the source region.
1. A semiconductor integrated circuit device, comprising:
an SOI substrate comprising an insulating film laminated on a semiconductor support substrate and a semiconductor thin film laminated on the insulating film;
a first N-channel MOS transistor disposed on a surface of the semiconductor thin film;
a first P-channel MOS transistor disposed on the surface of the semiconductor thin film, the first P-channel MOS transistor being isolated from the first N-channel MOS transistor by a field insulating film;
a resistor formed on the field insulating film, the resistor and the semiconductor thin film being formed of single-crystal silicon; and
a second N-channel MOS transistor serving as an electrostatic discharge (ESD) protection element disposed on a surface of the semiconductor support substrate that is exposed by removing a part of the semiconductor thin film and a part of the insulating film, the second N-channel MOS transistor having a gate electrode, a source region, a drain region surrounding the source region through the gate electrode to maintain a constant distance between the drain region and the source region, and an impurity diffusion layer disposed in an outer periphery of the drain region and spaced apart a preselected distance from the drain region.
2. A semiconductor integrated circuit device according to claim 1 ; wherein the source of the second N-channel MOS transistor has a circular configuration.
3. A semiconductor integrated circuit device according to claim 1 ; wherein the source of the second N-channel MOS transistor has an elliptical configuration.
4. A semiconductor integrated circuit device according to claim 1 ; wherein the source of the second N-channel MOS transistor has a polygonal configuration.
5. A semiconductor integrated circuit device according to claim wherein 1 ; wherein a gate electrode of the first N-channel MOS transistor has an N-type conductivity and a gate electrode of the first P-channel MOS transistor has a P-type conductivity.
6. A semiconductor integrated circuit device according to claim 5 ; wherein each of the N-type gate electrode of the first N-channel MOS transistor, the P-type gate electrode of the first P-channel MOS transistor, and the gate electrode of the second N-channel MOS transistor is formed of a first polysilicon.
7. A semiconductor integrated circuit device according to claim 5 ; wherein each of the N-type gate electrode of the first N-channel MOS transistor, the P-type gate electrode of the first P-channel MOS transistor, and the gate electrode of the second N-channel MOS transistor has a laminate polycide structure of polysilicon and a refractory metal silicide.
8. A semiconductor integrated circuit device according to claim 1 ; wherein the semiconductor thin film forming the SOI substrate has a thickness in the range of 0.05 μm to 0.2 μm.
9. A semiconductor integrated circuit device according to claim 1 ; wherein the insulating film forming the SOI substrate has a thickness in the range of 0.1 μm to 0.5 μm.
10. A semiconductor integrated circuit device according to claim 1 ; wherein the insulating film forming the SOI substrate is made of an insulating material including glass, sapphire, and ceramics including a silicon oxide film and a silicon nitride film.
11. A semiconductor integrated circuit device comprising:
a semiconductor support substrate;
an insulating film disposed on the semiconductor support substrate;
a semiconductor thin film disposed on the insulating film;
a first N-channel MOS transistor and a P-channel MOS transistor disposed on the semiconductor thin film and isolated from each other by a field insulating film, and a resistor disposed on the field insulating film, the resistor and the semiconductor thin film being formed of single-crystal silicon; and
an electrostatic discharge (ESD) protection element having a second N-channel MOS transistor disposed on the semiconductor support substrate, the second N-channel MOS transistor having a gate electrode, a source region and a drain region surrounding the source region through the gate electrode so as to maintain a constant distance between the drain region and the source region in order to obtain a preselected holding voltage of the first N-channel MOS transistor that prevents a bipolar action of the first N-channel MOS transistor from occurring at a lower voltage than that of the second N-channel MOS transistor, and an impurity diffusion layer disposed in an outer periphery of the drain region and spaced apart a preselected distance from the drain region.
12. A semiconductor integrated circuit device according to claim 11 ; wherein the source of the second N-channel MOS transistor has one of a circular-, elliptical-, and polygonal-shaped configuration.
13. A semiconductor integrated circuit device according to claim 11 ; wherein a gate electrode of each of the first N-channel MOS transistor and the P-channel MOS transistor and the gate electrode of the second N-channel MOS transistor is formed of a first polysilicon; and wherein the resistor is formed of a second polysilicon having a thickness different from that of the first polysilicon.
14. A semiconductor integrated circuit device according to claim 11 ; wherein a gate electrode of each of the first N-channel MOS transistor and the P-channel MOS transistor and the gate electrode of the second N-channel MOS transistor has a laminate polycide structure of polysilicon and a refractory metal silicide.
15. A semiconductor integrated circuit device comprising:
an SOI substrate having a semiconductor support substrate, an insulating film disposed on the semiconductor support substrate, and a semiconductor thin film disposed on the insulating film;
an internal circuit element having a first N-channel MOS transistor and a P-channel MOS transistor each formed on the semiconductor thin film and isolated from each other by a field insulating film;
a resistor element formed on the field insulating film, the resistor and made of single-crystal silicon comprising the semiconductor thin film being formed of single-crystal silicon; and
an electrostatic discharge (ESD) protection element that performs an ESD protection operation and is formed on the semiconductor substrate, the ESD protection element having a second N-channel MOS transistor including a source region, a drain region surrounding the source region so that a voltage of the ESD protection element at a start of an ESD protection operation is controlled to a voltage lower than a withstand voltage of the internal circuit element, and an impurity diffusion layer disposed in an outer periphery of the drain region and spaced apart a preselected distance from the drain region.
16. A semiconductor integrated circuit device according to claim 15 ; wherein the drain region surrounds the source region so as to maintain a constant distance between the drain region and the source region.
17. A semiconductor integrated circuit device according to claim 15 ; wherein the source of the second N-channel MOS transistor has one of a circular-, elliptical-, and polygonal-shaped configuration.