Semiconductor integrated circuit device
View Patent ↗A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.
1. A semiconductor integrated circuit device comprising:
a plurality of circuit blocks, each of the plurality of circuits blocks having operating states which include at least a first state and a second state; and
a power management block including a memory which stores a maximum chip power, said maximum chip power being referred when one of the operating states for each of the plurality of circuit blocks is determined,
wherein each of the plurality of circuit blocks operates according to a respective function thereof in the first state and stops operating in the second state,
wherein the power management block changes the maximum chip power according to a temperature of the semiconductor integrated circuit device and determines one of the operating states for each of the plurality of circuit blocks so as not to exceed the maximum chip power.
2. A semiconductor integrated circuit device according to claim 1 ,
wherein the operating states of each of the plurality of circuit blocks further include a third state, in which each of the plurality of circuit blocks operates at a lower frequency than the first state.
3. A semiconductor integrated circuit device according to claim 1 ,
wherein the power management block determines one of the operating states of each of the plurality of circuit blocks based on a power consumption thereof in the first state and a power consumption which is necessary to transition to the first state.
4. A semiconductor integrated circuit device according to claim 1 ,
wherein each of the plurality of circuit blocks includes a leakage current control circuit controlling power consumption by a leakage current and a charging/discharging power control circuit controlling by charging/discharging of a load, and
wherein power consumption of each of the plurality of circuit blocks is controlled in accordance with the operating state for each of the plurality of circuit blocks by the leakage current control circuit and the charging/discharging power control circuit.
5. A semiconductor integrated circuit device according to claim 4 , further comprising:
a clock distribution system,
wherein the charging/discharging power control circuit of each of the plurality of circuit blocks controls power consumption by charging/discharging of a load via controlling the clock frequency distributed to each of the plurality of circuit blocks.
6. A semiconductor integrated circuit device according to claim 1 , wherein the memory is a non-volatile memory.
7. A semiconductor integrated circuit device according to claim 1 , further comprising:
a power table storing power values for each of the operating states for each of the plurality of circuit blocks.
8. A semiconductor integrated circuit device comprising:
a plurality of circuit blocks, each of the plurality of circuits blocks having operating states which include at least a first state and a second state; and
a power management block including a memory which stores a maximum chip power, said maximum chip power being referred when one of the operating states for each of the plurality of circuit blocks is determined,
wherein each of the plurality of circuit blocks operates at a lower frequency in the first state than in the second state,
wherein the power management block changes the maximum chip power according to a temperature of the semiconductor integrated circuit device and determines one of the operating states for each of the plurality of circuit blocks so as not to exceed the maximum chip power.
9. A semiconductor integrated circuit device according to claim 8 ,
wherein the power management block determines one of the operating states of each of the plurality of circuit blocks based on a power consumption thereof in the first state and a power consumption which is necessary to transition to the first state.
10. A semiconductor integrated circuit device according to claim 8 ,
wherein each of the plurality of circuit blocks includes a leakage current control circuit controlling power consumption by a leakage current and a charging/discharging power control circuit controlling by charging/discharging of a load,
wherein power consumption of each of the plurality of circuit blocks is controlled in accordance with the operating state for each of the plurality of circuit blocks by the leakage current control circuit and the charging/discharging power control circuit.
11. A semiconductor integrated circuit device according to claim 10 , further comprising:
a clock distribution system,
wherein the charging/discharging power control circuit of each of the plurality of circuit blocks controls power consumption by charging/discharging of a load via controlling the clock frequency distributed to each of the plurality of circuit blocks.
12. A semiconductor integrated circuit device according to claim 8 , wherein the memory is a non-volatile memory.
13. A semiconductor integrated circuit device according to claim 8 , further comprising:
a power table storing power values for each of the operating states for each of the plurality of circuit blocks.