Array substrate for liquid crystal display device and method of manufacturing the same
View Patent ↗An array substrate for a liquid crystal display device includes a substrate, a gate line on the substrate, a data line crossing the gate line to define a pixel region, a thin film transistor including a gate electrode, an active layer, an ohmic contact layer, a buffer metallic layer, a source electrode and a drain electrode, the thin film transistor being electrically connected to the gate line and the data line and a pixel electrode in the pixel region and connected to the thin film transistor, wherein the active layer is disposed over and within the gate electrode.
1. An array substrate for a liquid crystal display device, comprising:
a substrate;
a gate line on the substrate;
a data line crossing the gate line to define a pixel region;
a thin film transistor including a gate electrode, an active layer, an ohmic contact layer, a buffer metallic layer, a source electrode and a drain electrode, the thin film transistor being electrically connected to the gate line and the data line, wherein the data line is formed of a same layer as the buffer metallic layer; and
a pixel electrode in the pixel region and connected to the thin film transistor,
wherein the active layer is disposed over and within the gate electrode.
2. The array substrate according to claim 1 , wherein the pixel electrode, the source electrode and the drain electrode are formed of a same material and on a same layer.
3. The array substrate according to claim 2 , wherein the pixel electrode, the source electrode, and the drain electrode are formed of one of indium tin oxide, indium zinc oxide and indium tin zinc oxide.
4. The array substrate according to claim 1 , further comprising an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern under the data line.
5. The array substrate according to claim 4 , wherein the intrinsic amorphous silicon pattern and the impurity-doped amorphous silicon pattern have substantially a same width as the data line.
6. The array substrate according to claim 1 , further comprising an auxiliary pattern covering the data line, the auxiliary pattern including a transparent conductive material.
7. The array substrate according to claim 6 , wherein the auxiliary pattern is connected to the source electrode.
8. The array substrate according to claim 6 , further comprising an insulation layer formed on the auxiliary pattern, the thin film transistor and the pixel electrode.
9. The array substrate according to claim 6 , further comprising a gate pad, a data pad, a gate pad electrode, and a data pad electrode, wherein the gate pad is disposed at one end of the gate line, the data pad is disposed at one end of the data line, the gate pad electrode contacts the gate pad, and the data pad electrode contacts the data pad, wherein the data pad electrode is connected to the auxiliary pattern.
10. The array substrate according to claim 1 , wherein the buffer metallic layer is disposed between the ohmic contact layer and each of the source and drain electrodes.
11. The array substrate according to claim 1 , wherein the active layer has an island shape.
12. The array substrate according to claim 1 , wherein the pixel electrode overlaps with the gate line to form a storage capacitor, wherein the gate line functions as a first electrode of the storage capacitor and the pixel electrode functions as a second electrode of the storage capacitor.