IP Library Granted Patent US 8,422,668
Granted Patent B1
US 8,422,668 · App. 11/639,683 · Granted Apr 16, 2013

Table lookup operation on masked data

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Quick Facts
Patent No.
US 8,422,668
App. No.
11/639,683
Filed
Dec 15, 2006
Granted
Apr 16, 2013
Kind
B1
Art Unit
2438
USPC
380/28
Abstract

Processing of masked data using table lookups is described. A mask is applied to input data to generate masked input data. The mask and the masked input data are used in combination to locate an entry in a lookup table. The entry corresponds to a transformed version of the input data.

Claims (30)

1. A data processing method comprising:

applying a mask to input data to generate masked input data;

transforming said masked input data into transformed data using byte substitution implemented using a lookup table (LUT);

for mask correction of said transformed data, using said masked input data and said mask in combination to locate an entry in said LUT, said entry corresponding to a transformed and unmasked version of said input data,

wherein said masked input data is mapped to said entry in said LUT using an M-to-N decoder that is controlled by said mask, where M is the number of bits in said masked input data and N is the number of entries in said LUT, wherein outputs of said M-to-N decoder are provided as inputs to a cascade of multiplexers, wherein each of said multiplexers is controlled according to a value of a corresponding bit of said mask; and

inverting a value of a bit in an output of said M-to-N decoder if a corresponding bit in said mask has a first value, wherein if said corresponding bit has a second value then said bit of said output is not inverted.

2. The method of claim 1 wherein said LUT is implemented in read only memory.

3. The method of claim 1 wherein said LUT is implemented in hardware as synthesized logic.

4. The method of claim 1 wherein said M-to-N decoder comprises a cascade of two-to-two decoders, wherein said cascade comprises a two-to-two decoder comprising a de-multiplexer having two outputs, wherein both said outputs are provided as inputs to each of two multiplexers, and wherein both said multiplexers are controlled according to a value of a corresponding bit of said mask.

5. The method of claim 1 wherein first access logic is used for said byte substitution and second access logic different from said first access logic is used for said mask correction.

6. The method of claim 5 wherein said second access logic comprises a first multiplexer whose output is provided to a plurality of multiplexers, and wherein said first access logic bypasses said plurality of multiplexers.

7. A data processing method comprising:

applying a first mask to first input data to generate first masked input data;

applying a second mask to second input data to generate second masked input data, wherein said second mask is different from said first mask;

transforming said first masked input data into transformed data using byte substitution implemented using a lookup table (LUT); and

for mask correction of said transformed data, using said first mask and said first masked input data to locate a first entry in said LUT, said first entry corresponding to a transformed and unmasked version of said first input data;

using said second mask and said second masked input data to locate a second entry in said LUT, said second entry corresponding to a transformed version of said second input data, wherein said first masked input data and said second masked input data are respectively mapped to said first and second entries in said LUT using an M-to-N decoder that is controlled respectively by said first and second masks, where M is the number of input bits and N is the number of entries in said LUT; and

inverting a value of a bit in an output of said M-to-N decoder if a corresponding bit in a corresponding mask has a first value, wherein if said corresponding bit has a second value then said bit of said output is not inverted.

8. The method of claim 7 wherein said M-to-N decoder comprises a cascade of two-to-two decoders, wherein said cascade comprises a two-to-two decoder comprising a de-multiplexer having two outputs, wherein both said outputs are provided as inputs to each of two multiplexers; wherein to locate said first entry, outputs of both said multiplexers are selected according to a value of a corresponding bit of said first mask; and wherein to locate said second entry, outputs of both said multiplexers are selected according to a value of a corresponding bit of said second mask.

9. The method of claim 7 wherein outputs of said M-to-N decoder are provided as inputs to a cascade of multiplexers; wherein to locate said first entry, outputs of each of said multiplexers are selected according to a value of a corresponding bit of said first mask; and wherein to locate said second entry, outputs of each of said multiplexers are selected according to a value of a corresponding bit of said second mask.

10. A data processing system comprising:

a mask generator comprising an XOR gate operable for generating a mask that is applied to input data to generate masked input data; and

a decoder comprising a cascade of de-multiplexers and a cascade of multiplexers interleaved with said cascade of de-multiplexers,

said decoder coupled to said mask generator and operable for transforming said masked data into transformed data using byte substitution implemented by accessing a lookup table (LUT),

said decoder also operable for identifying an entry in said LUT using said masked input data and said mask in combination, said entry corresponding to a transformed and unmasked version of said input data;

wherein a value of a bit in an output of said decoder is inverted if a corresponding bit in a corresponding mask has a first value, wherein if said corresponding bit has a second value then said bit of said output is not inverted.

11. The system of claim 10 wherein said LUT is implemented in read only memory.

12. The system of claim 10 wherein said LUT is implemented in hardware as synthesized logic.

13. The system of claim 10 wherein said de-multiplexers include a de-multiplexer having two outputs, wherein both said outputs are provided as inputs to each of two multiplexers and wherein both of said two multiplexers are controlled according to a value of a corresponding bit of said mask.

14. The system of claim 10 further comprising a second cascade of multiplexers downstream of said decoder, wherein outputs of said decoder are provided as inputs to said multiplexers in said second cascade and wherein each of said multiplexers in said second cascade is controlled according to a value of a corresponding bit of said mask.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →