Serial data transfer in a numerically controlled control system to update an output value of the control system

1. A method for a serial data transfer in a numerically controlled control system to update an output value of the control system, wherein the method comprises:

determining bits of a current data word, which have to be updated to ensure that the current data word will be provided after the serial data transfer, and

generating a receive signal according to a number of bits, which has to be transferred for updating the data word, to start and to end the data transfer and to update the output value of the control system;

wherein the number of bits, which only has to be transferred for updating the data word, depends on a location of a bit value in a data word which has to be altered and has a biggest distance to an input of an input shift register of a variable write depth shift register.

2. Method according to claim 1 , further comprising a variable write depth shift register receives only a number of bits according to the location of a bit in a data word, which has to be altered and has the biggest distance to the input of an input shift register of the variable write depth shift register.

3. Method according to claim 1 , wherein the location of a bit in a data word is selected in such a way that more frequently alternating bit values are arranged near to the input of an input shift register of the variable write depth shift register.

4. Method according to claim 1 , further comprising a receive signal is used to determine start and end of a data serial transfer of bits from a data source to update a data word from a previous data word and enables the update of bit values of a control word at the output of the variable write depth shift register, which have to be altered for updating the data word or output value of the control system.

5. Arrangement for a serial data transfer in a numerically controlled control system to update an output value of the control system, comprising a variable write depth shift register for enabling a number of outputs of a latch register of the variable write depth shift register to be updated when a data transfer from a data source to the variable write depth shift register terminates, which corresponds to a number of received clock pulses writing bit values into an input shift register of the variable write depth shift register for updating the output value or data word at the output of the variable write depth shift register from a previous output value or data word and for keeping bit values of a data word at the output of the variable write depth shift register, which not have to be altered to provide the updated output value or data word at the output of the variable write depth shift register.

6. Arrangement according to claim 5 , wherein the variable write depth shift register comprises an input shift register, a latch register and an enable shift register, which ensures that in cases, where only some bits of a data word near to the input of the input register have to be updated to form a desired data word, that only said bit values are latched via the latch register to the output of the variable write depth shift register for updating the data word and avoids that bit values of further stages of the input register, which not have been updated occur at the output of the variable write depth shift register.

7. Arrangement according to claim 5 , wherein the variable write depth shift register comprises an input shift register, a latch register, a counter and a decoder, which ensures that in cases, where only some bits of a data word near to the input of the input register have to be updated to form a desired data word, that only said bit values are latched via the latch register to the output of the variable write depth shift register for updating the data word and avoids that bit values of further stages of the input register, which not have been updated occur at the output of the variable write depth shift register.

8. Arrangement according to claim 5 , wherein the input shift register is a serial data receiving shift register and the latch register has clock inputs each connected to an output of an And gate having a fist input connected to a line providing a receive signal and a second input connected to an output of an enabler for latching a number of outputs of the input shift register to an output of the variable write depth shift register according to a number of clock pulses received to fed at least on bit value into the input shift register.

9. A variable write depth shift register comprising a serial data receiving input shift register, a latch register and an enabler for counting a number of clock pulses or bit values fed into the input shift register to determine a write depth of the variable write depth shift register, for updating a status of a corresponding number of stages of the latch register and for keeping a status of remaining stages of the latch register.